Effect of size and position of gold nanocrystals embedded in gate oxide of SiO_(2)/Si MOS structures  

作　　者：Chaitali Chakraborty Chayanika Bose 

机构地区：[1]Department of Electronics and Telecommunications Engineering Jadavpur University,Kolkata–700032,India

出　　处：《Journal of Advanced Dielectrics》2016年第1期34-38,共5页先进电介质学报（英文）

摘　　要：The influence of single and double layered gold(Au)nanocrystals(NC),embedded in SiO_(2) matrix,on the electrical characteristics of metal–oxide–semiconductor(MOS)structures is reported in this communication.The size and position of the NCs are varied and study is made using Sentaurus TCAD simulation tools.In a single NC-layered MOS structure,the role of NCs is more prominent when they are placed closer to SiO_(2)/Si-substrate interface than to SiO_(2)/Al–gate interface.In MOS structures with larger NC dots and double layered NCs,the charge storage capacity is increased due to charging of the dielectric in the presence of NCs.Higher breakdown voltage and smaller leakage current are also obtained in the case of dual NC-layered MOS device.A new phenomenon of smearing out of the capacitance–voltage curve is observed in the presence of dual NC layer indicating generation of interface traps.An internal electric field developed between these two charged NC layers is expected to generate such interface traps at the SiO_(2)/Si interface.

关 键 词：NANOCRYSTALS MOS capacitance-voltage curve leakage current 

分 类 号：TN3[电子电信—物理电子学]