基于Wishbone总线的并行全交换通信设计和实现  

Design and Implementation of Parallel All Switch Based on Wishbone Bus

作　　者：王纲领 陈敏 刘远 WANG Gangling;CHEN Min;LIU Yuan(No.30 Institute of CETC,Chengdu Sichuan 610041,China)

机构地区：[1]中国电子科技集团公司第三十研究所,四川成都610041

出　　处：《信息与电脑》2022年第15期37-40,共4页Information & Computer

摘　　要：针对高速、超高速多板卡、多芯片的通信需求,提出基于Wishbone总线的并行全交换通信技术。该技术采用交叉开关型Wishbone总线的多端任意互联设计,通过自定义的通信帧协议,实现了通信带宽达到10 Gbit/s的高速并行全交换通信。本设计具有去中心化、实现简单、资源占用率少等显著特点。文中给出的基于现场可编程逻辑门阵列(Field Programmable Gate Array,FPGA)的仿真和实现方案,进一步体现了多通道并行全交换和广播通信的设计性能。To meet the requirements of high-speed,ultra-high-speed multi-board and multi-chip communication,a parallel all-switched communication technology based on Wishbone bus is proposed.This technology adopts cross-switch Wishbone bus multi-terminal arbitrary interconnection design.High-speed parallel full switch communication with bandwidth up to 10 Gbit/s through the self-defined protocol is realized.This design has the characteristics of decentralization,simple implementation and low resource occupancy.The simulation and implementation based on Field Programmable Gate Array(FPGA)embodies the design’s performance of multi-channel parallel full switch and broadcast switch.

关 键 词：WISHBONE 全交换 高速并行 

分 类 号：TN915.05[电子电信—通信与信息系统]