应用于时钟发生器的低杂散亚采样锁相环  

Low spur sub-sampling PLL applied to clock generator

作　　者：杜佳恒 赵宏亮[1] 刘兴辉[1] 程帅 赵日新[1,2,3] 赵野 DU Jiaheng;ZHAO Hongliang;LIU Xinghui;CHENG Shuai;ZHAO Rixin;ZHAO Ye(School of Physics,Liaoning University,Shenyang 110036,China;Institute of Microelectronics of Chinese Academy of Sciences,Beijing 100029,China;Key Laboratory of Science and Technology on Silicon Devices,Chinese Academy of Sciences,Beijing 100029,China)

机构地区：[1]辽宁大学物理学院,辽宁沈阳110036 [2]中国科学院微电子研究所,北京100029 [3]中国科学院硅器件技术重点实验室,北京100029

出　　处：《传感器与微系统》2022年第12期87-89,94,共4页Transducer and Microsystem Technologies

基　　金：国家重点研发计划“新能源汽车专项”项目(2016YFB0100516)。

摘　　要：设计了一种应用于高精度时钟发生器的低杂散亚采样锁相环(SSPLL)电路。得益于亚采样锁相环锁定时核心环路中没有分频器的存在,带内噪声得到明显的抑制;同时由于采用了大环路带宽,从而也抑制了环形振荡器所主导的带外噪声;使用虚拟采样器消除了二进制频移键控(BFSK)效应,降低了参考杂散;利用单位增益缓冲器和隔离缓冲器进一步降低了参考杂散;改进的可调窄死区发生器有助于锁定时间加快。本文亚采样锁相环基于110 nm CMOS工艺设计,仿真结果表明:电路整体功耗为7.3 mW,锁定时间小于4μs,锁定后输出电压纹波仅为0.42 mV,在75 MHz的频偏处参考杂散为-72.15 dBc。A low spur sub-sampling phase-locked loop(SSPLL)for high precision clock generator is presented.The in-band noise is significantly suppressed due to the absence of the frequency divider in the core loop when the SSPLL is locked.At the same time, the out-of-band noise dominated by the ring oscillator is suppressed because of large loop bandwidth.Dummy sampler is used to eliminate binary frequency shift keying(BFSK) effect and the reference spur is reduced.The unit gain buffer and the isolation buffer are used to further reduce the reference spur.The improved tunable narrow dead zone creator helps to accelerate the locking time.The SSPLL is designed based on 110 nm CMOS process.The simulation results show that the power consumption of circuit is 7.3 mW,the locking time is less than 4 μs, and the output voltage ripple after locking is only 0.42 mV.The reference spur at 75 MHz frequency offset is -72.15 dBc.

关 键 词：低杂散 亚采样 锁相环 二进制频移键控效应 

分 类 号：TN402[电子电信—微电子学与固体电子学]