基于RISC-V架构的Zephyr SMP的研究与实现  

Research and Implementation of Zephyr SMP on RISC-V

作　　者：朱绍英 顾云鹭 查启鹏 ZHU Shao-ying;GU Yun-lu;ZHA Qi-peng(Shanghai Civil Aviation College,Shanghai 200232,China;Intel Asia Pacific R&D Ltd,Shanghai 201100,China)

机构地区：[1]上海民航职业技术学院,上海200232 [2]英特尔亚太研发有限公司,上海201100

出　　处：《电脑与信息技术》2022年第6期51-54,64,共5页Computer and Information Technology

基　　金：民航发展基金(项目编号:14003700000018J002)。

摘　　要：RISC-V架构由于其精简和模块化的指令集以及更开放的授权而广泛用于设计各种处理器,而Zephyr操作系统目前只支持单CPU的RISC-V,缺少对高性能多CPU的SMP应用处理器的支持。为此,首先从RISC-V架构的特点和Zephyr的编译,启动等方面分析了移植Zephyr的过程,然后从三个方面分析了支持SMP的具体设计原理和实现流程,包括Zephyr SMP定义的底层架构接口实现,SMP线程切换和调度的实现和SMP相关驱动的实现。最后,在开发板上测试结果表明SMP下的多线程启动及延迟,线程抢占和唤醒均符合Zephyr设计。RISC-V is a modular RISC instruction set which is highly optimized to reduce hardware complexity and is open for all organization to design processors,while latest Zephyr RTOS only support single CPU and doesn’t support multi SMP CPUs for RISC-V.To solve this limitation,it introduces how to port Zephyr to HiFive board with detail build and bring up steps.then analyzes how to support SMP in aspects of implementation of Zephyr SMP low level interfaces for each architecture,implementation of thread context switch and schedule,improvement of interrupt and timer driver for SMP.Finally,module test shows that thread boot and scheduling,thread preemption and wakeup works as expected in Zephyr.

关 键 词：RISC-V Zephyr实时操作系统 对称多处理 线程调度 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]