高速总线控制芯片故障定位与失效机理研究  

Research on Fault Location and Failure Mechanism of High- speed Bus Control Chip

作　　者：王敦 潘硕 韩兆芳 苏龙 罗永波 WANG Dun;PAN Shuo;HAN Zhao-fang;SU Long;LUO Yong-bo(China Key System&Integrated Circuit Co.,Ltd.,Wuxi 214000,China)

机构地区：[1]中科芯集成电路有限公司,江苏无锡214000

出　　处：《航空计算技术》2022年第6期112-115,共4页Aeronautical Computing Technique

基　　金：国家自然科学基金项目资助(52101055)。

摘　　要：随着对数据传输能力要求不断提高,高速总线控制芯片的可靠性越来越受到关注,针对高速控制总线芯片在设计验证阶段失效问题进行分析,通过故障定位方法,系统研究了芯片在设计、封装及测试验证过程中的影响因素,确定芯片失效位置及机理,为总线控制电路过应力EOS防护设计提供参考,保证芯片在高速传输过程中的数据稳定以及低误码率。With the continuous improvement of the requirements for data transmission capacity,the reliability of high-speed bus control chip has attracted more and more attention.Based on the analysis of the failure of high-speed control bus chip in the design verification stage,this paper systematically studies the influencing factors of the chip in the process of design,packaging and test verification through the fault location method,determines the chip failure location and mechanism,and provides a reference for the design of over stress EOS protection of bus control circuit.Ensure the data stability and low bit error rate of the chip in the process of high-speed transmission.

关 键 词：高速总线 控制芯片 应用故障分析 失效机理 

分 类 号：TN492[电子电信—微电子学与固体电子学]