基于数字阵列的干扰机架构研究  

A Study on of Jammer Architecture Based on Digital Array

作　　者：李圣衍[1] 黄海波 江涛[1] 吴志乾 LI Shengyan;HUANG Haibo;JIANG Tao;WU Zhiqian(Nanjing Research Institute of Electronics Technology,Nanjing 210039,China)

机构地区：[1]南京电子技术研究所,南京210039

出　　处：《现代雷达》2022年第10期72-77,共6页Modern Radar

摘　　要：简要分析了常规相控阵干扰的架构、特点以及存在的问题,并借鉴当前数字阵雷达的架构,提出了一种全数字阵干扰机架构,对该干扰机架构、系统组成、功能实现和关键技术等进行了分析,最后指出该架构在工程应用上存在的问题及后续改进的方向。The application of phased array technology is widely more and more in ECM field, currently the common phased array jammer can work that is guided by ESM device, and realize tasks of HGESM & HPECM,but It has certain limitations. The architecture and the feature and existed problem of common phased array jammer is analysed, draw on the experience of digital array radar architecture, a kind of architecture of full digital array jammer is proposed, and the jammer architecture and system form and function realization and key technology is analysed, finally existed problem of project application and follow-up improvement direction about the architecture is pointed out.

关 键 词：高增益电子侦察 高功率电子干扰 数字射频存储器 数字波束形成 模拟相控阵 数字阵列 

分 类 号：TN972[电子电信—信号与信息处理]