基于RISC-V调试协议的片上调试系统设计与实现  

Design and implementation of on-chip debugging system based on RISC-V debugging protocol

作　　者：许霁航 杨靓[1] 娄冕[1] 张海金[1] XU Jihang;YANG Liang;LOU Mian;ZHANG Haijin(Xi′an Microelectronics Technology Institute,Xi′an 710054,Shaanxi,China)

机构地区：[1]西安微电子技术研究所,陕西西安710076

出　　处：《微电子学与计算机》2022年第12期86-92,共7页Microelectronics & Computer

基　　金：航天科技集团青年拔尖项目(YY2022-015)。

摘　　要：为满足RISC-V架构生态中对RISC-V平台软件调试的需求,设计并实现了一种基于RISC-V调试协议的片上调试系统.该系统通过调试传输模块实现并隐藏调试模块内部寄存器访问逻辑,将其简化为JTAG串行信号实现与宿主机的交互,并通过调试模块实现了调试所必需的处理器全面监控与存储访问功能.在基本调试功能的基础上,进一步实现了总线直接访问、程序缓存和基于触发模块的触发功能,并在兼容RISC-V调试协议的情况下实现了事件序列触发功能.该片上调试系统依托于自研RISC-V处理器硬件平台,通过GDB与OpenOCD构成的宿主机软件环境进行功能测试.经过与其他RISC-V架构处理器对比和FPGA测试表明,该片上调试系统功能丰富,能够满足目前RISC-V平台调试的功能需求.In order to meet the needs of RISC-V platform software debugging in the RISC-V architecture ecosystem,an on-chip debugging system based on the RISC-V debugging protocol is designed and implemented.The system implements and hides the internal register access logic of the debug module through the debug transport module,and simplifies it into a JTAG serial signal to implements the interaction with the host computer.On the basis of the basic debugging function,the direct bus access,program buffer and trigger function based on the trigger module are further implemented,and implements the event sequence trigger function while being compatible with the RISC-V debugging protocol.The on-chip debugging system relies on the self-developed RISC-V processor hardware platform,and performs functional testing through the host software environment composed of GDB and OpenOCD.The comparison with other RISC-V architecture processors and FPGA tests show that the on-chip debugging system is rich in functions and can meet the functional requirements of the current RISC-V platform debugging.

关 键 词：RISC-V 软件调试 远程调试 触发模块 

分 类 号：TN47[电子电信—微电子学与固体电子学]