并口EEPROM芯片研发中的验证策略研究  

Research on verification strategy in parallel port EEPROM chip development

作　　者：况野 李国 阙旻 余葛伟 杨东坪 KUANG Ye;LI Guo;QUE Min;YU Ge-wei;YANG Dong-ping(Chengdu Sino Microelectronics Technology Co.,Ltd.)

机构地区：[1]成都华微电子科技股份有限公司

出　　处：《中国集成电路》2022年第12期38-42,共5页China lntegrated Circuit

摘　　要：EEPROM(Electrically Erasable Programmable Read-Only Memory)存储芯片是目前数字设备中常用的存储器件,其中支持并口传输的EEPROM传输速度快、性能更好,受到更多用户的青睐。与此同时,EEPROM存储芯片除了存储阵列容量大,其内部控制逻辑复杂、时序的可容忍偏差小、地址译码繁杂、状态及设计困难、地址遍历验证非常耗时,且随容量的提升呈指数级增加,这就对项目的质量和进度产生重要影响。因此,通过多种措施提升EDA仿真验证平台的能力和效率,缩短验证时间,提高验证完备性,已经成为并口EEPROM存储芯片研发过程中的痛点和难点。本文以实际工作中并口EEPROM存储芯片的研发过程为依托,对基于UVM仿真平台的验证策略展开研究,为提高此类芯片的研发效率提供经验参考。EEPROM(Electrically Erasable Programmable Read Only Memory)memory chip is a commonly used memory device in digital devices at present.EEPROM supporting parallel port transmission has fast transmission speed and better performance,which is favored by more users.At the same time,in addition to the large storage array capacity,the EEPROM memory chip has complex internal control logic,small tolerable timing deviation,complex address decoding,difficult status and design,and very time-consuming address traversal verification.With the growth of capacity,these problems increase exponentially,which has an important impact on the quality and progress of the project.Therefore,improving the capability and efficiency of EDA simulation and verification platform through various measures,shortening the verification time and improving the verification completeness have become the pain and dif-ficulty in the research and development of parallel EEPROM memory chips.Based on the research and development process of parallel port EEPROM memory chip in practical work,this paper studies the verification strategy based on UVM simulation platform,and provides experience reference for improving the research and development efficiency of this kind of chip.

关 键 词：并口EEPROM EDA验证 UVM 随机延时 覆盖率 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] TN40[自动化与计算机技术—计算机科学与技术]