基于数字孪生技术的晶圆级测试平台  

Wafer Level Test Platform Based on Digital Twin Technology

作　　者：李斌[1] 胡晓霞[1,2] 吕磊 王进瑞[2] LI Bin;HU Xiaoxia;LÜ Lei;WANG Jinrui(The 45th Research Institute of CETC,Beijing 100176,China;Sanhe Wuatech Co.,Ltd.,Yanjiao 065201,China)

机构地区：[1]中国电子科技集团公司第四十五研究所,北京100176 [2]三河建华高科有限责任公司,河北燕郊065201

出　　处：《电子工业专用设备》2022年第5期32-35,46,共5页Equipment for Electronic Products Manufacturing

摘　　要：从数字孪生技术以及晶圆级测试现状出发,根据数字孪生技术需求,详细介绍了数字化晶圆级测试系统构建内容,进行了系统搭建,并对数字孪生技术在本领域后续发展方向进行了展望。Starting from the current situation of digital twin technology and wafer level testing,based on the requirements of digital twin technology,introduces the construction content of digital wafer level testing system in detail,and making the test system establishment,furthermore looking forward to the follow-up development direction of digital twin technology in this field.

关 键 词：数字孪生 半导体 晶圆级测试 

分 类 号：TN305.1[电子电信—物理电子学]