5G低轨卫星两步随机接入方案及其FPGA实现  

Two-step Random Access Scheme of 5G LEO Satellite and Its FPGA Implementation

作　　者：梁震 崔高峰[1] 王卫东[1] LIANG Zhen;CUI Gaofeng;WANG Weidong(School of Electronic Engineering,Beijing University of Posts and Telecommunications,Beijing 100876,China)

机构地区：[1]北京邮电大学电子工程学院,北京100876

出　　处：《电讯技术》2022年第12期1758-1765,共8页Telecommunication Engineering

基　　金：国家自然科学基金资助项目(61971054);京津冀协同创新共同体建设专项(19240407D)。

摘　　要：为了实现低轨卫星通信系统高效率低时延的用户接入,提出了适用于低轨卫星系统的两步随机接入方案,对随机接入信道的数据发送、信道结构、前导码设计以及映射关系进行了设计,并进行了现场可编程门阵列(Field Programmable Gate Array,FPGA)实现。针对传统MAX-LOG-MPA算法FPGA处理时延长的问题,提出了一种节点并行迭代更新的FPGA接收机设计来降低处理时延。仿真结果验证了所设计的信道结构以及FPGA实现的可行性,相比传统接入方式可接入的用户数量更多,同时采用并行节点迭代更新的接收机将迭代处理时延降低为1/6。In order to realize the user access of low earth orbit(LEO)satellite communication system with high efficiency and low delay,a two-step random access scheme for LEO satellite system is proposed.In this scheme,the data transmission,channel structure,preamble design and mapping relationship of random access channel are designed and implemented on field programmable gate array(FPGA).For the problem of FPGA processing time delay of traditional MAX-LOG-MPA algorithm,an FPGA receiver design with node parallel iterative update is proposed to reduce the processing delay.The simulation results verify the feasibility of the designed channel structure and FPGA implementation.Compared with the traditional access method,the number of users that can be accessed is more.At the same time,the iteratively updated receiver using parallel nodes reduces the iterative processing delay to 1/6.

关 键 词：低轨卫星 随机接入 信道设计 稀疏码分多址接入(SCMA) FPGA并行处理 

分 类 号：TN927.2[电子电信—通信与信息系统]