DS6-60全电子联锁模拟试验分析  

Analysis of DS6-60 Full Electronic Interlocking Simulation Test

作　　者：侯礼举 刘洪光 Hou Liju;Liu Hongguang(CRSC Urban Rail Transit Technology Co.,Ltd.,Beijing 100070,China)

机构地区：[1]通号城市轨道交通技术有限公司,北京100070

出　　处：《铁路通信信号工程技术》2022年第12期74-79,共6页Railway Signalling & Communication Engineering

基　　金：通号城市轨道交通技术有限公司科研项目(2020J03)。

摘　　要：针对全电子联锁输入/输出电子模块化的特点,从工程实际应用出发,研发适用于全电子联锁的模拟试验设备、方法及步骤,进一步优化联锁试验,最大限度地减少信号系统调试的工作量。实际工程应用证明,通过采用联锁模拟试验的方式,可以快速有效地发现软件潜在问题以及硬件配线错误,确保联锁关系正确性,为工程顺利实施提供有力保障。对全电子联锁模拟试验进行全面、系统、详细的说明,并重点对联锁模拟电路进行分析和研究。According to the characteristics of electronic modularization of full electronic interlocking input/output,starting from the practical engineering application,the simulation test equipment,methods and steps suitable for full electronic interlocking are developed,the interlocking test is further optimized,and the workload of signaling system commissioning is reduced to the greatest extent.The actual engineering application shows that the potential software problems and wrong hardware wirings can be found quickly and effectively by interlocking simulation test,so as to ensure the correctness of the interlocking relationship and provide a strong guarantee for the smooth implementation of the project.This paper gives a comprehensive,systematic and detailed description of the full electronic interlocking simulation test,and focuses on the analysis and research of the interlocking simulation circuit.

关 键 词：全电子联锁 输入/输出模块 模拟电路 联锁试验 

分 类 号：U284.3[交通运输工程—交通信息工程及控制]