检索规则说明:AND代表“并且”;OR代表“或者”;NOT代表“不包含”;(注意必须大写,运算符两边需空一格)
检 索 范 例 :范例一: (K=图书馆学 OR K=情报学) AND A=范并思 范例二:J=计算机应用与软件 AND (U=C++ OR U=Basic) NOT M=Visual
作 者:罗万先 LUO Wanxian(Guangzhou Chuangtian Electronic Technology Co.,Ltd.,Guangzhou 510700,China)
机构地区:[1]广州创天电子科技有限公司,广东广州510700
出 处:《现代信息科技》2022年第23期38-39,43,共3页Modern Information Technology
摘 要:在压敏电阻器发展及使用过程中,围绕对小体积低容值片式压敏电阻器的工艺制造技术方向进行可行性分析,对材料配方、烧结技术和产品表面绝缘处理等关键技术进行了研究,报告了压敏电阻器国内生产技术水平和国外同行压敏电阻器的研发发展现状,简单概括了小体积低容值片式压敏电阻器产品的结构设计、参数设计、工艺路线研究方向、产品的应用方向(如:产品的响应速度和高集成化),挖掘各层次存在的技术风险和进度风险问题展开分析,提出解决方案和思路,降低风险系数;对片式压敏电阻的制造工艺进行分解介质材料配方、产品表面绝缘处理关键技术进行了探讨。During the development and use of varistors,around the feasibility analysis of the process manufacturing technology direction of small volume low capacitance chip varistors,the key technologies such as material formulation,sintering technology and product surface insulation treatment are studied,and the domestic production technology level of varistors and the development status of foreign counterparts'varistors are reported.The structural design,parameter design,process route research direction and product application direction(such as product response speed and high integration)of small volume low capacitance chip varistor products are briefly summarized.The technical risk and schedule risk problems existing at all levels are analyzed,and solutions and ideas are proposed to reduce the risk coefficient.The decomposition of the dielectric material formula of the manufacturing process of the chip varistor and the key technologies of surface insulation treatment of the product are discussed.
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在链接到云南高校图书馆文献保障联盟下载...
云南高校图书馆联盟文献共享服务平台 版权所有©
您的IP:3.20.233.121