应用于时间数字转换器的补偿校准算法及电路  

A compensation algorithm and calibration circuit for time-to-digital converter

作　　者：赵捷 赵野[1,3] 童纪昀 王莎 张孟翟 赵发展 ZHAO Jie;ZHAO Ye;TONG Jiyun;WANG Sha;ZHANG Mengdi;ZHAO Fazhan(Institute of Microelectronics,Chinese Academy of Sciences,Beijing 100029,China;University of Chinese Academy of Sciences,Beijing 100029,China;Key Laboratory of Science and Technology on Silicon Devices,Chinese Academy of Sciences,Beijing 100029,China)

机构地区：[1]中国科学院微电子研究所,北京100029 [2]中国科学院大学,北京100029 [3]中国科学院硅器件技术重点实验室,北京100029

出　　处：《合肥工业大学学报（自然科学版）》2022年第12期1637-1642,共6页Journal of Hefei University of Technology：Natural Science

基　　金：国家重点研发计划新能源汽车专项资助项目(2016YFB0100516)。

摘　　要：文章提出一种基于相位内插型时间数字转换器(time-to-digital converter, TDC)的补偿算法及校准电路,通过该电路能有效地解决由于亚稳态和PVT(process,voltage and temperature)因素变化引起的TDC的采样错误,并且不需要额外的计数器、锁频电路或基于统计方法学的复杂结构。基于该方法的TDC电路采用CMOS 0.110μm工艺设计实现,版图面积仅为380×140μm^(2),在1.2 V电源下功耗为4.2 mW。仿真结果表明:系统分辨率为104 ps,最大微分非线性(differential nonlinearity,DNL)和积分非线性(integral nonlinearity,INL)分别为0.3、2.5 LSB,证明依据该算法的TDC电路具有良好的时间精度和线性度。A compensation algorithm and calibration circuit based on phase interpolation time-to-digital converter(TDC)is proposed.The circuit can effectively solve the sampling error of TDC caused by metastable state and process,voltage and temperature(PVT),and does not need additional counter,frequency locking circuit or complex structure based on statistical methodology.The TDC circuit based on this method is designed and implemented in CMOS 0.110μm process,the layout area is only 380×140μm^(2),and the power consumption is 4.2 mW under 1.2 V power supply.The simulation results show that the system resolution is 104 ps,the maximum differential nonlinearity(DNL)and integral nonlinearity(INL)are 0.3 LSB and 2.5 LSB,respectively,which proves that the TDC based on this algorithm has good time precision and linearity.

关 键 词：时间数字转换器(TDC) 相位内插 补偿校准 亚稳态 算法电路 

分 类 号：TN402[电子电信—微电子学与固体电子学]