p-GaN HEMT器件动态栅应力下的性能退化机理  

Performance degradation mechanism of p-GaN HEMT under dynamic gate stress

作　　者：黄静雯 李胜 张弛 刘斯扬[1] 孙伟锋[1] Huang Jingwen;Li Sheng;Zhang Chi;Liu Siyang;Sun Weifeng(National ASIC System Engineering Research Center,Southeast University,Nanjing 210096,China)

机构地区：[1]东南大学国家专用集成电路系统工程技术研究中心,南京210096

出　　处：《东南大学学报（自然科学版）》2022年第6期1130-1136,共7页Journal of Southeast University：Natural Science Edition

基　　金：国家重点研发计划资助项目(2020YFF0218501)。

摘　　要：为了研究p型栅氮化镓高电子迁移率晶体管(p-GaN HEMT)在动态栅应力下的电学特性退化机理,设计了一种双管控制快速切换测试电路,在施加动态栅应力后300 ns内快速测量器件的导通电阻,并进行了对比实验和仿真分析.结果表明,在施加300 s有效动态栅应力后,器件的阈值电压基本保持不变,而导通电阻随应力施加时间、频率的增大呈明显增加趋势,且退化率最高达到10.82%.在器件的开启、关断阶段,空穴热载流子会注入到沟道层,最终导致器件导通电阻的退化;但是在导通持续、关断持续阶段由于没有热载流子产生,该应力下器件电学参数保持稳定.综上,器件导通电阻在动态栅应力下的退化主要是由开启、关断阶段的空穴热载流子注入引起的.To study the electrical performance degradation mechanism of gallium nitride based p-type gate high electron mobility transistor(p-GaN HEMT)under dynamic gate stress,a fast switching test circuit controlled by two switching devices is designed,and the dynamic on-state resistance(R)of the device under test(DUT)is rapidly measured within 300 ns after the dynamic gate stress is applied.Furthermore,comparative experiments combined with simulation analysis are conducted.The results show that when the effective dynamic gate stress is applied for 300 s,the threshold voltage of DUT remains basically unchanged,while the Rincreases significantly with the increase of the time and the frequency of the stress,and the highest degradation rate reaches up to 10.82%.Hole hot carriers are injected into the channel layer of DUT during turn-on and turn-off stages,eventually leading to the degradation of R.However,due to the absence of hot carriers during the on-state and off-state procedures,the electrical parameters of the device remain stable.In conclusion,the Rdegradation under dynamic gate stress is mainly induced by the hole hot carrier injection during turn-on and turn-off stages.

关 键 词：p-GaN HEMT 测试电路 动态栅应力 导通电阻退化 

分 类 号：TN386[电子电信—物理电子学]