一种高线性度的2.4 GHz CMOS功率放大器设计  

Design of a 2.4 GHz CMOS power amplifier with high linearity

作　　者：王家文 潘文光 Wang Jiawen;Pan Wenguang(School of Microelectronics,University of Chinese Academy of Sciences,Beijing 100049,China;Nanjing Zhongke Microelectronics Co.,Ltd.,Nanjing 210018,China)

机构地区：[1]中国科学院大学微电子学院,北京100049 [2]南京中科微电子有限公司,江苏南京210018

出　　处：《电子技术应用》2022年第12期65-69,共5页Application of Electronic Technique

摘　　要：为了满足目前物联网低成本、低功耗与较高线性度的市场应用需求,提出了一种高线性度的2.4 GHz功率放大器(PA)。该功率放大器为两级结构,为了提高增益的同时保持较低的静态功耗其驱动级采用了电流复用两级共源放大结构,并且使用了两级失真抵消的方法减小了晶体管跨导非线性的影响,同时采用二极管线性化偏置来补偿寄生电容非线性导致的增益压缩现象。该功率放大器采用0.18μm CMOS工艺,后仿真结果表明,在2.4 GHz工作频率下,该PA小信号增益为30 dB,输出1 dB压缩点为22 dBm,静态功耗为53 mW,功率附加效率峰值为31%。In order to meet the market demand of low-cost,low-power consumption and high linearity of the Internet of Things,a 2.4 GHz power amplifier(PA)with high linearity is proposed.The power amplifier has a two-stage structure.In order to improve the gain while maintaining low static power consumption,the driver stage of the PA adopts a current multiplexing two-stage common source amplifier structure,uses a two-stage distortion cancellation method to reduce transconductance nonlinearity,and adopts diode linearization bias to compensate gain compression phenomenon caused by parasitic capacitance nonlinearity.The PA uses a 0.18μm CMOS process.Simulation results show that at 2.4 GHz operating frequency,the PA has a small signal gain of 30 dB,an output 1 dB compression point of 21.7 dBm,a static power consumption of 53 mW,and a power-added efficiency peak of 31%.

关 键 词：功率放大器 电流复用 失真抵消 二极管线性化偏置 

分 类 号：TN722[电子电信—电路与系统]