基于FPGA的XG-PON OLT侧上行BCDR实现  

Implementation of XGPON OLT Uplink BCDR Based on FPGA

作　　者：陈荣观 陈传前 CHEN Rongguan;CHEN Chuanqian(Fujian i-Star Technology Co.,Ltd.,Fuzhou 350001,China)

机构地区：[1]福建星网智慧科技有限公司,福建福州350001

出　　处：《电声技术》2022年第9期117-122,共6页Audio Engineering

摘　　要：在10 Gb·s^(-1)无源光网络(10-Gigabit-capable Passive Optical Network,XG-PON)应用中,满足新标准和产品及时面市的要求非常重要,但是更需要降低系统成本和功耗。在无源光网络(Passive Optical Network,PON)环境中,突发时钟数据恢复(Burst Clock Data Recovery,BCDR)是关键的光线路终端(Optical Line Termination,OLT)组件,它的效率直接影响PON线路的上行效率。迄今为止,国产现场可编程门阵列(Field-Programmable Gate Array,FPGA)还没有集成BCDR的解决方案。对此,提出一种基于收发器的FPGA,采用全同步过采样技术,实现XG-PON BCDR。该方案符合ITU-T G.987和ITU-T G.989标准,可以移植到没有集成BCDR的FPGA中,降低系统成本和功耗。In the application of 10 Gb·s^(-1)Passive Optical Network(XG-PON), it is very important to meet the new standards and timely product launch requirements, but it is more important to reduce the system cost and power consumption. In Passive Optical Network(PON) environment, Burst Clock Data Recovery(BCDR) is the key Optical Line Termination(OLT), whose efficiency directly affects the uplink efficiency of the PON line. To date, there is no domestic Field-Programmable Gate Array(FPGA) solution that integrates BCDR. This paper proposes an FPGA based on transceiver, which adopts fully synchronous over-sampling technology to realize XG-PON BCDR. It conforms to ITU-T G.987 and ITU-T G.989 standards, and can be transplanted to FPGA without BCDR integration to reduce system cost and power consumption.

关 键 词：现场可编程门阵列(FPGA) 10 Gb·s^(-1)无源光网络(XG-PON) 突发时钟数据恢复(BCDR) 光线路终端(OLT) 

分 类 号：TN914[电子电信—通信与信息系统]