LP-LDPC:Three-Level Parallel FPGA Architecture for Fast Prototyping of LDPC Decoder Using High-Level Synthesis  

作　　者：Yi-Fan Zhang Lei Sun Qiang Cao 张一凡;孙磊;曹强(Wuhan National Laboratory for Optoelectronics,Wuhan 430074,China)

机构地区：[1]Wuhan National Laboratory for Optoelectronics,Wuhan 430074,China

出　　处：《Journal of Computer Science & Technology》2022年第6期1290-1306,共17页计算机科学技术学报（英文版）

基　　金：the National Key Research and Development Program of China under Grant No.2018YF-A0701800;the National Natural Science Foundation of China under Grant Nos.61821003 and 62172175,and Alibaba Group through Alibaba Innovative Research(AIR)Program.

摘　　要：Low-Density Parity-heck Codes(LDPC)with excellent error-correction capabilities have been widely used in both data communication and storage fields,to construct reliable cyber-physical systems that are resilient to real-world noises.Fast prototyping field-programmable gate array(FPGA)-based decoder is essential to achieve high decoding performance while accelerating the development process.This paper proposes a three-level parallel architecture,TLP-LDPC,to achieve high throughput by fully exploiting the characteristics of both LDPC and underlying hardware while effectively scaling to large-size FPGA platforms.The three-level parallel architecture contains a low-level decoding unit,a mid-level multi-unit decoding core,and a high-level multi-core decoder.The low-level decoding unit is a basic LDPC computation component that effectively combines the features of the LDPC algorithm and hardware with the specific structure(e.g.,Look-Up-Table,LUT)of the FPGA and eliminates potential data conflicts.The mid-level decoding core integrates the input/output and multiple decoding units in a well-balancing pipelined fashion.The top-level multi-core architecture conveniently makes full use of board-level resources to improve the overall throughput.We develop an LDPC C++code with dedicated pragmas and leverage HLS tools to implement the TLP-LDPC architecture.Experimental results show that TLP-LDPC achieves 9.63 Gbps end-to-end decoding throughput on a Xilinx Alveo U50 platform,3.9x higher than existing HLS-based FPGA implementations.

关 键 词：low-density parity-check(LDPC) high-level synthesis(HLS) field-programmable gate array(FPGA) 

分 类 号：TN91[电子电信—通信与信息系统]