用于CZT探测器前端的数字自校准SAR-ADC设计  

Design of SAR-ADC with digital self-calibration for CZT detectors front-ends

作　　者：刘伟 郭尚尚 商世广 Liu Wei;Guo Shangshang;Shang Shiguang(School of Electronic Engineering,Xi'an University of Posts and Telecommunications,Xi'an 710121,China)

机构地区：[1]西安邮电大学电子工程学院,西安710121

出　　处：《电子测量与仪器学报》2022年第9期167-173,共7页Journal of Electronic Measurement and Instrumentation

基　　金：陕西省自然科学基础研究计划(2020JM-583);陕西省教育厅重点科学研究计划-协同创新项目(21JY039)资助。

摘　　要：为了满足碲锌镉(CZT)探测器前端读出系统对模数转换器(ADC)的特殊需求,设计实现了一款12 bit 1.6 MS/s的前台数字自校准逐次逼近型(SAR)ADC。采用先校准后正常输出的工作方式以提高数据转换的实时性,校准模式下,SAR-ADC核心部分对差分斜坡输入电压注入低幅值扰动,再利用最小均方(LMS)自适应算法在数字域对亚二进制电容权重进行校准并固定;正常工作模式下,按照已经校准的权重值正常输出数字码。搭建数模混合仿真平台进行仿真验证,结果表明,当时钟信号频率为20 MHz,输入信号频率为239.1 kHz时,校准后与校准前相比,SAR-ADC的信噪失真比(signal-to-noise and distortion ratio, SNDR)由45.59 dB提升到了72.35 dB,有效位数(effective number of bit, ENOB)由7.28 bit提升到了11.73 bit, SAR-ADC性能明显提升,前端读出电路与SAR-ADC的联合线性度δ为-0.29%~0.34%,能够满足CZT探测器前端读出系统的使用需求。In order to meet the special requirements of the front-end readout system of cadmium zine telluride(CZT) detector for analog to digital converter(ADC), a foreground digital self-calibration successive approximation register(SAR) ADC with 12 bit 1.6 MS/s is presented. The working mode of calibration followed by output is adopted to improve the real-time performance of data conversion. In the calibration mode, the core part of SAR-ADC injects low amplitude disturbance to the differential ramp input voltage, then uses the least mean square(LMS) adaptive algorithm to calibrate and fix the Sub-radix-2 capacitance weight in the digital domain. In the normal working mode, the digital code is output normally according to the calibrated weight value. A digital-analog hybrid simulation platform is built for simulation and verification. The results show that when the clock signal frequency is 20 MHz and the input signal frequency is 239.1 kHz, the signal-to-noise and distortion ratio(SNDR) of SAR-ADC after calibration is increased from 45.59 dB to 72.35 dB, and the effective number of bit(ENOB) is increased from 7.28 bit to 11.73 bit. The performance of SAR-ADC is obviously improved, and the linearity δ between front-end readout circuit and SAR-ADC is-0.29%~0.34%, which can meet the requirements of CZT detector front-end readout system.

关 键 词：探测器 模数转换器 校准 最小均方(LMS) 

分 类 号：TN453[电子电信—微电子学与固体电子学] TN432