检索规则说明:AND代表“并且”;OR代表“或者”;NOT代表“不包含”;(注意必须大写,运算符两边需空一格)
检 索 范 例 :范例一: (K=图书馆学 OR K=情报学) AND A=范并思 范例二:J=计算机应用与软件 AND (U=C++ OR U=Basic) NOT M=Visual
作 者:马毅超[1] 王施敏 庄建 李嘉杰[2,3] MA Yi-chao;WANG Shi-min;ZHUANG Jian;LI Jia-jie(School of Electrical and Control Engineering,Shaanxi University of Science and Technology,Xi'an Shaanxi 710021,China;Spallation Neutron Source Science Center,Dongguan Guangdong 523803,China;Institute of High Energy Physics,Chinese Academy of Sciences,Beijing 100049,China)
机构地区:[1]陕西科技大学电气与控制工程学院,陕西西安710021 [2]散裂中子源科学中心,广东东莞523803 [3]中国科学院高能物理研究所,北京100049
出 处:《核电子学与探测技术》2022年第2期328-333,共6页Nuclear Electronics & Detection Technology
基 金:国家自然科学基金项目(U1832117);核探测与核电子学国家重点实验室项目(SKLPDE-ZZ-202103)资助。
摘 要:为满足同步和多技术扫描的要求,基于FPGA实现一种BISS协议编码器处理平台,提供同步触发和数据捕获功能,是探测器扫描位置触发的关键技术.硬件部分的电路是由FPGA、差分芯片SN75179B和IC-MHM绝对值编码器组成的,软件部分是基于FPGA的时钟产生模块、解码模块和CRC校验模块的设计.通过软硬件测试对IC-MHM编码器信号进行处理,仿真和实测结果表明基于FPGA设计的BISS接口符合BISS协议的时序,能够准确接收和处理编码器数据.In order to meet the requirements of synchronous and multi technology scanning,a BISS protocol encoder processing platform based on FPGA provides synchronous triggering and data acquisition functions,which is the key technology of detector scanning position triggering.The circuit of the hardware part is composed of FPGA,differential chip SN75179B and IC-MHM absolute value encoder.The software part is the design of clock generation module,decoding module and CRC verification module based on FPGA.The IC-MHM encoder signal is processed through software and hardware testing.The simulation and measured results show that the BISS interface designed based on FPGA conforms to the timing of BISS protocol and can accurately receive and process encoder data.
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在载入数据...
正在链接到云南高校图书馆文献保障联盟下载...
云南高校图书馆联盟文献共享服务平台 版权所有©
您的IP:216.73.216.70