基于互补电阻开关的忆阻乘法器设计  

Design of Memristive Multiplier Based on Complementary Resistive Switch

作　　者：李志刚 陈辉 刘鹏 武继刚[1] LI Zhigang;CHEN Hui;LIU Peng;WU Jigang(School of Computer and Technology,Guangdong University of Technology,Guangzhou 510006,China)

机构地区：[1]广东工业大学计算机学院,广州510006

出　　处：《计算机工程》2023年第1期201-209,共9页Computer Engineering

基　　金：国家自然科学基金“忆阻交叉阵列高质量低费用测试方法研究”(62174038);广东省基础与应用基础研究基金“利用多种读写机制和忆阻器逻辑设计的阻性存储器高速测试方法研究”(2019A1515110284)。

摘　　要：现有的忆阻算术逻辑多采用单个忆阻器作为存储单元,在忆阻交叉阵列中易受到漏电流以及设计逻辑电路时逻辑综合复杂度高的影响,导致当前乘法器设计中串行化加法操作的延时和面积开销增加。互补电阻开关具有可重构逻辑电路的运算速度和抑制忆阻交叉阵列中漏电流的性能,是实现忆阻算术逻辑的关键器件。提出一种弱进位依赖的忆阻乘法器。为提升忆阻器的逻辑性能,基于互补电阻开关电路结构,设计两种加法器的优化方案,简化操作步骤。在此基础上,通过改进传统的乘法实现方式,并对进位数据进行拆解,降低运算过程中进位数据之间的依赖性,实现并行化的加法运算。将设计的乘法器映射到混合CMOS/crossbar结构中,乘法计算性能得到大幅提高。在Spice仿真环境下验证所提乘法器的可行性。仿真实验结果表明,与现有的乘法器相比,所提乘法器的延时开销从O(n2)降低为线性级别,同时面积开销降低约70%。The existing memristive arithmetic logic primarily uses a single memristor as the storage unit,which is vulnerable to leakage currents in the memristor cross array and the high complexity of logic synthesis in a logic circuit design;consequently,increased delays and area overheads will be indicated in the serial addition operation of the current multiplier design.A Complementary Resistive Switch(CRS)is a key device for realizing the memristive arithmetic logic as it can reconfigure the logic circuit operation speed and restrains leakage currents in a memristor cross array.A memristive multiplier with weak carry dependency is proposed herein.To improve the logic performance of the memristor,based on the circuit structure of the CRS,two types of optimization schemes for the adder are designed to simplify the operation steps.Subsequently,by improving the classical multiplication method and disassembling the carry data,the dependency between carry data during the operation is reduced,and a parallel addition operation is realized.By mapping the designed multiplier to a hybrid CMOS/crossbar structure,the performance of multiplication computation is improved significantly.The feasibility of the proposed multiplier is verified in a Spice simulation environment.The simulation results show that compared with the existing multiplier,the proposed multiplier reduces the delay cost from O(n~2)to the linear level and reduces the area cost by approximately 70%.

关 键 词：忆阻器 互补电阻开关 混合CMOS/crossbar结构 加法器 乘法器 

分 类 号：TP331.2[自动化与计算机技术—计算机系统结构]