一种基于FPGA的高速并行传输系统设计  

Design of a High-Speed Parallel Transmission System Based on FPGA

作　　者：毕涛 刘迪 张大为 葛宝川 BI Tao;LIU Di;ZHANG Dawei;GE Baochuan(School of Basic Science for Aviation,Naval Aviation University,Yantai 264001,China)

机构地区：[1]海军航空大学航空基础学院,山东烟台264001

出　　处：《现代信息科技》2023年第1期58-60,63,共4页Modern Information Technology

摘　　要：该系统使用FPGA芯片完成了高速并行传输系统设计,其由并行数据发送端、并行数据信道、并行数据接收端和数据分析显示装置四部分构成。并行数据发送端实现海明编码和数据格式转变的功能;并行数据信道由7根同轴电缆及相应电路组成;接收端进行故障检测、数据同步提取、抽样判决和校验纠错。在传输过程中实时监测数据状态,最后通过RS232串口发送给PC机用于检测误码率。系统创新地使用了“多采样点判决算法”,降低了传输过程中的误码率。This system uses FPGA chip to complete the design of high-speed parallel transmission system.The system consists of four parts:parallel data sending end,parallel data channel,parallel data receiving end and data analysis and display device.The parallel data sending end realizes the functions of Hamming coding and data format transformation.The parallel data channel is composed of 7 coaxial cables and corresponding circuits.The receiving end performs fault detection,data synchronous extraction,sampling decision and check and error correction.In the transmission process,the data status is monitored in real time,and finally sent to the PC through RS232 serial port for detecting the bit error rate.The system innovatively uses the“multi sampling point decision algorithm”to reduce the bit error rate in the transmission process.

关 键 词：现场可编门阵列 并行数据传输 误码率 海明码 串行通信 

分 类 号：TP274.2[自动化与计算机技术—检测技术与自动化装置]