集成电路设计与EDA技术课程专业能力培养实践——RTL设计的层次化展平处理  

Integrated Circuit Design and EDA Technology Course Professional Ability Training Practice——RTL Design Hierarchical Flattening Processing

作　　者：杨怡雯 曾梓萱 赵岩[1] 李长庚[1] YANG Yiwen;ZENG Zixuan;ZHAO Yan;LI Changgeng(School of Physics and Electronics,Central South University,Changsha 410083,China)

机构地区：[1]中南大学物理与电子学院,湖南长沙410083

出　　处：《现代信息科技》2023年第2期171-173,177,共4页Modern Information Technology

基　　金：湖南省教学改革省级课题(HNJG-2021-0302);中南大学教学改革校级课题(2021jy063)。

摘　　要：VerilogHDL作为描述数字电路的通用语言,在大规模设计中一般采用层次化和结构化的设计方法。为了在获得较优的电路面积结果的同时提高综合后输出网表的可读性,使用Python和正则表达式对Verilog代码进行层次化展平处理,用模块内的设计代码替换实例化语句。打平层次结构后,设计代码变为没有层次的、不带参数、不带可选择配置的扁平链式结构,提高了代码的可维护性。此实践项目难度适中,有助于学生深入理解Verilog HDL的语法结构和EDA软件的工作原理,提高了学生的设计实践能力。As a general language for describing digital circuits,Verilog HDL generally adopts hierarchical and structured design methods in large-scale designs.In order to obtain better circuit area results while improving the readability of the synthesized output netlist,Python and regular expressions are used to hierarchically flatten the Verilog code,replacing instantiated statements with in-module design code.After flattening the hierarchical structure,the design code became a flat chain structure without hierarchy,parameters,optional configuration,which improves the maintainability of the code.The difficulty of this practice project is moderate,which helps students to deep understand the grammatical structure of Verilog HDL and the working principle of EDA software,and improves students’design practice ability.

关 键 词：正则表达式 PYTHON 代码扁平化 课程教学 

分 类 号：TP39[自动化与计算机技术—计算机应用技术] G434[自动化与计算机技术—计算机科学与技术]