可变截止频率的高斯滤波器在FPGA中的实现  

Implementation of Variable Cut-off Frequency Gaussian Filter in FPGA

作　　者：房子皓 Fang Zi-hao(School of Mechatronic Engineering,Xi’an Technological university,Xi’an 710021,China)

机构地区：[1]西安工业大学机电工程学院,西安710021

出　　处：《内燃机与配件》2023年第1期71-73,共3页Internal Combustion Engine & Parts

摘　　要：为了解决高斯滤波设计到FPGA后,所确定的截止频率需要更换高斯模板才能更改的缺点,提出一种基于FPGA的可变截止频率高斯滤波器设计方法。该滤波器在高斯模板不变的情况下,控制传入高斯模板的频率来改变输出信号的截止频率,通过Verilog语言实现设计,并在SoC齿轮测量机系统中实验验证结果。结果表明:该滤波器滤除噪声的同时能较好的保留有效信号,在不更换高斯模板的情况下可方便调节信号的截止频率。In order to solve the problem that the cut-off frequency can only be changed by changing the Gaussian template after the Gaussian filter is designed to FPGA, a design method of variable cut-off frequency Gaussian filter based on FPGA is proposed. The filter controls the frequency of the incoming Gaussian template to change the cut-off frequency of the output signal when the Gaussian template is unchanged. It is designed by Verilog language, and the results are verified by experiments in the SoC gear measuring machine system. The results show that the filter can not only filter out the noise but also retain the effective signal. The cut-off frequency of the signal can be easily adjusted without changing the Gaussian template.

关 键 词：FPGA 可变频 截止频率 高斯模板 

分 类 号：TN713[电子电信—电路与系统] TN431.2