自适应跨平台PSS中间件架构及开发  

Self-adapting midware architecture & development for cross-platform PSS

作　　者：王锋 王磊 张栗榕 Wang Feng;Wang Lei;Zhang Lirong(Xi′an R&D Institute,New H3C Semiconductor,Xi′an 710075,China)

机构地区：[1]新华三半导体技术有限公司西安研究所,陕西西安710075

出　　处：《电子技术应用》2023年第1期20-25,共6页Application of Electronic Technique

摘　　要：芯片工艺、规模不断在提升,所包含的功能越来越复杂。多核、多线程中央处理器(Central Processing Unit,CPU),多维度片上网络(Network on Chip,No C),高速、高密度接口,各类外设等IP(Intellectual Property)集成在芯片上系统(System on Chip,So C),使芯片开发阶段的仿真验证场景极其复杂,对芯片特别是So C开发和验证完备性带来巨大挑战。当前在芯片开发领域,便携式测试和激励标准(Portable Test and Stimulus,PSS)是在UVM(Universal Verification Methodology)验证方法学基础上进一步解决随机化和跨平台的复杂组合场景定义和代码生成难题。但目前的PSS标准有一定局限,例如还不支持汇编语言,也无法自适应地调用不同型号、不同平台的验证IP(Verification IP,VIP)等,影响在芯片验证中全面部署PSS。提出一种新的验证平台(Verification Platform)架构,即在PSS场景模型和测试台(Testbench,TB)层之间实现一层中间件(Midware),支持自动生成汇编语言测试代码以及自适应地调用VIP和AVIP(Accelerated VIP)等,以充分发挥PSS高层场景建模的优势,实现芯片验证灵活、高效和完备性的统一。With continuous evolution of semiconductor process technologies and IC(Integrated Chip) scales,more and more complex functions are integrated.Multi-core multi-thread CPU(Central Processing Unit),multi-dimension NoC(Network on Chip),high speed interfaces,kinds of peripherals and so on IP(Intellectual Property) are integrated into SoC(System on Chip).As a result,verification scenarios during IC development become extremely complicated,which leads to great challenges to the SoC development and corresponding verification completeness.Currently PSS(Portable Test Stimulus Standard) has been introduced along with the UVM(Universal Verification Methodology) for generating extensive randomized stimulus with more complicated scenarios.However,the PSS standard,as of today,doesn′t support generating assembly test code and invoking different VIP(Verification IP) flexibly.In order to solve these problems mentioned above,we introduce a verification platform architecture by implementing a new layer as midware between the PSS model and the testbench.The Midware layer can give full play to the PSS advantages of high-level scenes modeling and achieve the flexibility,efficiency and completeness of chip verification.

关 键 词：芯片 PSS 中间件 验证 VIP 

分 类 号：TN402[电子电信—微电子学与固体电子学]