一种应用于CMOS图像传感器的列级高精度ADC设计  

A Column-level High Resolution ADC Design for CMOS Image Sensor

作　　者：张为森 马艳华[1] 曲杨 常玉春[1] ZHANG Weisen;MA Yanhua;QU Yang;CHANG Yuchun(School of Microelectronics,Dalian University of Technology,Dalian 116600,CHN)

机构地区：[1]大连理工大学微电子学院,辽宁大连116000

出　　处：《半导体光电》2022年第5期867-872,共6页Semiconductor Optoelectronics

基　　金：国家重点研发计划项目(2019YFB2204101);工信部产业技术基础公共服务平台项目(CEIEC-2020-ZM02-0093/4)。

摘　　要：针对CMOS图像传感器高精度和低功耗的需求,设计了一种14位列级模数转换器(ADC)。在传统斜坡式模数转换器(RAMP ADC)架构基础上,采用了3位逐次逼近型模数转换器(SAR ADC)与11位RAMP ADC相结合的两步式结构,有效缩短了量化时间。RAMP ADC部分采用高低时钟的计数方法,可显著降低计数区间内的功耗。同时,提出了RAMP-SAR-RAMP切换的相关双采样逻辑,可进一步减少静态随机存取存储器(SRAM)数量,从而缩小版图面积。采用0.18μm标准CMOS工艺进行仿真,结果表明:在600 MHz时钟、单沿计数的工作模式下,ADC量化时间为9.32μs,在1.8 V数字电源电压下,计数区间内功耗均值为8.51μW。Aiming at the requirements of high precision and low power consumption for CMOS image sensor, a 14 bit column-level ADC was proposed. Based on the architecture of RAMP ADC, the two-step structure composed of 3-bit SAR ADC and 11-bit RAMP ADC was adopted, which reduced the quantization time effectively. In the module of RAMP ADC, the high-low clock counting method was employed to reduce the power consumption in the counting part. The correlated double sampling logic of RAMP-SAR-RAMP switch was proposed, which could decrease the number of SRAM and further reduce the layout area. Simulation results based on the 0.18 μm standard CMOS process show that under the working mode of 600 MHz clock and single edge counting, the quantization time of ADC is 9.32 μs, and the average power consumption in the counting part is 8.51 μW under the 1.8 V digital power supply.

关 键 词：SAR/RAMP ADC 两步式 高精度 量化时间 CMOS图像传感器 

分 类 号：TN47[电子电信—微电子学与固体电子学]