一种具有低噪声高电源抑制的LDO电路设计  

Design of a LDO Circuit with Low Noise and High Power Suppression

作　　者：王妍[1,2] 杨潇雨 魏林 赵之昱 WANG Yan;YANG Xiaoyu;WEI Ling;ZHAO Zhiyu(National Laboratory of Science and Technology on Analog Integrated Circuit,Chongqing400060,P.R.China;The 24th Research Institute of China Electronics Technology Corporation,Chongqing400060,P.R.China)

机构地区：[1]模拟集成电路国家级重点实验室,重庆400060 [2]中国电子科技集团公司第二十四研究所,重庆400060

出　　处：《微电子学》2022年第5期837-842,共6页Microelectronics

基　　金：国家自然科学基金资助项目(6142802190101)。

摘　　要：设计了一种基于28 nm CMOS工艺的低噪声高电源抑制LDO电路。采用折叠共源共栅结构设计了高输出阻抗、高增益误差的放大器,降低了电源噪声对输出端的影响。采用共源共栅密勒补偿结构,保证电路在负载处于轻载/重载下保持较高的相位裕度,增强了环路稳定性。误差放大器输入端采用降噪模块电路,降低了噪声对整体LDO电路的影响。基于Cadence Spectre进行仿真分析的结果表明,在1.9 V电源电压下,负载由轻载10 mA突变为重载60 mA时,环路增益为77.6~91 dB,相位裕度达到76°~79°。在中间负载电流30 mA下,对电源抑制(PSR)和噪声进行了仿真。结果表明,电源抑制为-81.9 dB,低频噪声(1 kHz)为258 nV·Hz^(-1/2)。对LDO整体电路进行了版图设计和后仿比对。结果表明,环路增益为83.2 dB,相位裕度为78°,PSR为-78.3 dB,低频噪声(1 kHz)为283 nV·Hz^(-1/2)。A low noise high PSR low dropout voltage(LDO) was designed in a 28 nm CMOS process. A folded cascode structure was adopted to design the high output impedance and high-gain error amplifier, which reduced the effect of power supply noise on the output. A cascode Miller compensation structure was used to ensure a high phase margin under both light and heavy load, enhancing the LDO loop stability. A noise reduction module was applied to the input of error amplifier, which reduced the impact of noise on the whole LDO circuit. The simulation and analysis with Cadence Spectre show that, under 1.9 V power supply voltage and the load varied from 10 mA to 60 mA, the loop gain is 77.6~91 dB, and the phase margin reaches 76°~79°. The power supply rejection(PSR) and noise were simulated under intermediate load current of 30 mA. The results show that the power supply rejection is-81.9 dB and the low frequency noise(1 kHz) is 258 nV· HZ^(-1/2). The layout design and post-imitation comparison of the whole LDO circuit were carried out. The results show that the loop gain is 83.2 dB, the phase margin is 78°, the PSR is-78.3 dB, and the low-frequency noise(1 kHz) is 283 nV· HZ^(-1/2).

关 键 词：28nm CMOS工艺 LDO 高电源抑制 低噪声 

分 类 号：TN432[电子电信—微电子学与固体电子学]