基于0.13μm SiGe工艺的48~68GHz四倍频器  

A 48~68 GHz Quadrupler Based on 0.13 μm SiGe Process

作　　者：赵振[1,2] 杨浩然 唐人杰 王卡楠 桂小琰 ZHAO Zhen;YANG Haoran;TANG Renjie;WANG Kanan;GUI Xiaoyan(The School of Electronic and Information Engineering,Xi’an JiaoTong University,Xi’an 710049,P.R.China;The School of Microelectronics,Xi’an JiaoTong University,Xi’an 710049,P.R.China)

机构地区：[1]西安交通大学电信学部,西安710049 [2]西安交通大学微电子学院,西安710049

出　　处：《微电子学》2022年第5期868-872,共5页Microelectronics

基　　金：国家自然科学基金资助项目(62174132)。

摘　　要：采用0.13μm SiGe BiCMOS工艺,设计并实现了一种应用于高速光通信的全集成注入锁定四倍频器芯片。该设计包括单端转差分放大器、注入锁定二倍频器(ILFD)以及分频器(Divider-by-2)。测试结果表明,该四倍频器的输出锁定范围达到了48~68 GHz,输出锁定在65 GHz时的谐波抑制比为36 dBc。芯片核心面积为0.36 mm^(2),在3.3 V供电电压下,核心功耗为247 mW。该设计可以满足下一代超高速光电互联芯片对高速时钟的应用需求。A fully integrated injection-locked quadrupler for high-speed optical communication was designed and implemented in a 0.13-μm SiGe BiCMOS process. The design included a single-to-differential amplifier, injection-locked frequency doublers, and a divider-by-2 for measurement purpose. The measurement result indicates that the quadrupler achieves an operation bandwidth from 48 to 68 GHz while the harmonic rejection ratio is 36 dBc when the output is locked at 65 GHz. The chip occupies a core area of 0.36 mm^(2), and the power consumption is 247 mW with a 3.3 V supply. The quadrupler can meet the requirements of high-speed sampling clock in the next-generation ultra-high-speed optical communication systems.

关 键 词：注入锁定 倍频器 四倍频器 锁定范围 

分 类 号：TN771[电子电信—电路与系统] TN433