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作 者:宋春伟 何金龙 李刚 SONG Chun-wei;HE Jin-long;LI Gang(College of Modern Science and Technology,China Jiliang University,Yiwu 322000,China)
机构地区:[1]中国计量大学现代科技学院,浙江义乌322000
出 处:《电机与控制学报》2023年第1期80-87,109,共9页Electric Machines and Control
基 金:浙江省自然科学基金(LY22E070008,LY20E070006);浙江省公益基金(LGG19E070004);浙江省高校领军人才培养计划。
摘 要:针对死区时间引起H桥拓扑各桥臂输出电压波形偏离给定参考电压的问题,根据一个开关周期内调制波与输出电流极性提出了具有12种导通状态的新型开关方式。基于新型开关方式提出了3H桥开关次数均匀分布死区消除SVPWM方案。以三相感应电机作为负载,推导出采用死区消除SVPWM后,在输出电流过零处工频与高频工作桥臂具有的天然死区时间。MCU输出各桥臂上下开关管相位互差180°SVPWM信号以及表征调制波与输出电流极性的电平信号,而后信号经FPGA处理后获得死区消除SVPWM信号。实验结果中给出了在相同参考电压下,采用死区消除SVPWM时输出电压最大偏离给定电压在1.3%左右,而采用有死区SVPWM时最大偏离给定电压在23%左右。由此可见,由MCU与FPGA相结合的数字系统能够很好地实现开关次数均衡死区消除SVPWM策略。In order to solve the problem that the output voltage waveform of each leg of H-bridge topology deviates from the given reference voltage due to the dead time, the novel on-off modes including twelve conduction states is presented in one switching period. Based on the novel on-off mode, the dead-time elimination SVPWM is presented with good switching times sharing effect. 3H bridge inverter adopts dead-time elimination SVPWM to drive a three-phase induction motor. This paper deduces the natural dead time at the zero crossing of output current when the leg is in the fundamental-frequency or high frequency operation state. MCU outputs SVPWM signals with 180° phase difference between upper and lower switches of each leg and the polarity signals of modulation wave and output current. After processing MCU output signals, FPGA outputs the dead-time elimination SVPWM signals. The experimental results show that the maximum deviation of the output voltage from the given voltage is about 1.3% with dead-time elimination SVPWM and about 23% with dead-time SVPWM under the same reference voltage. It can be seen that the effectiveness of the proposed dead-time elimination SVPWM with switching times sharing is verified by the digital system combined MCU and FPGA.
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