基于级间电容抵消技术的74~88 GHz高性能CMOS LNA设计  

Design of 74-88 GHz High Performance CMOS LNA Based on Interstage Capacitance Cancellation Technology

作　　者：康志谋 邹林峰 蒋欣怡 石春琦[1,2] 张润曦[1] KANG Zhimou;ZOU Linfeng;JIANG Xinyi;SHI Chunqi;ZHANG Runxi(Institute of Microelectronic Circuits and Systems,East China Normal University,Shanghai,200241,CHN;Key Laboratory of Multidimensional Information Processing,East China Normal University,Shanghai,200241,CHN)

机构地区：[1]华东师范大学微电子电路与系统研究所,上海200241 [2]华东师范大学上海市多维度信息处理重点实验室,上海200241

出　　处：《固体电子学研究与进展》2022年第6期484-491,共8页Research & Progress of SSE

基　　金：中央高校基本科研业务费专项资金资助(40500-20103-222178);上海市科委资助项目(18DZ2270800)。

摘　　要：采用55 nm CMOS工艺,面向毫米波雷达应用,设计了一款74~88 GHz高性能CMOS低噪声放大器(LNA)。该LNA应用共源共栅结构,为了改善噪声系数、提高稳定性增益,采用级间寄生电容抵消的电感反馈共栅短接技术和基于反相双圈耦合的等效跨导增强技术。和传统共栅短接技术相比,级间寄生电容抵消的电感反馈共栅短接技术改善噪声系数1.58 dB,提高稳定性增益7.67 dB。芯片测试结果表明,LNA峰值增益为17.1 dB,最小噪声系数为6.3 dB,3 dB带宽为14 GHz(74.8~88.8 GHz),在78 GHz中心频率处输入1 dB压缩点(IP1dB)为-10.2 dBm,功耗为102 mW。A 74-88 GHz high performance CMOS low noise amplifier(LNA)was designed and fabricated in 55 nm CMOS process for millimeter wave radar applications.The proposed LNA adopted cascode structure.In order to improve the noise figure and the stability gain,the inductive feedback common-gate-shorting technique with interstage parasitic capacitance cancellation and the out-of-phase dual-coupling gm-boosting technique were adopted.Compared with the traditional common grid shorting technology,the inductive feedback common grid shorting technology with interstage parasitic capacitance cancellation improves the noise figure by 1.58 dB and the stability gain by 7.67 dB.The measurement results show that the peak gain of the LNA is of 17.1 dB,the minimum noise figure is6.3 dB,the BW-3dBis 14 GHz(74.8-88.8 GHz).The input 1 dB compression point(IP1dB)is-10.2 dBm at a center frequency of 78 GHz while consuming 102 mW of power.

关 键 词：寄生电容抵消 低噪声放大器 反相双圈耦合 电感反馈共栅短接 

分 类 号：TN432[电子电信—微电子学与固体电子学]