星载多分区高速缓存技术研究  

Research on spaceborne multi-partition cache technology

作　　者：张俊杰 周浩 徐瑞瑞 顾德友 林海兵 ZHANG Junjie;ZHOU Hao;XU Ruirui;GU Deyou;LIN Haibing(Shanghai Aerospace Electronic Technology Institute,Shanghai 201109,China)

机构地区：[1]上海航天电子技术研究所,上海201109

出　　处：《长江信息通信》2023年第1期53-55,共3页Changjiang Information & Communications

摘　　要：针对星载终端产品载荷接口类型丰富、数据传输速率高的特点,提出一种基于宇航应用场景的多载荷分区的高速缓存技术。该方案采用Xilinx高性能FPGA作为主控芯片实现高速数据处理,采用高可靠宇航级DDR3芯片实现高速数据缓存,并采取了冗余校验的方式加强了可靠性。本设计数据缓存接口速率可达1066MT/s,能够对输入的10种载荷类型数据的进行动态缓存,设计吞吐率可达50Gbps。文章通过Modelsim仿真平台对系统功能进行了仿真验证,并给出了验证结果,结果表明该设计能够满足多载荷高速率的应用需求。Aiming at the characteristics of various load interface types and high data transmission rate of space-borne terminal products,a multi-load partition cache technology based on aerospace application scenario was proposed.In this scheme,Xilinx high performance FPGA is used as the main control chip to realize high-speed data processing,and highly reliable aerospace DDR3 chip is used to realize high-speed data caching,and redundancy check is adopted to strengthen the reliability.This design data cache interface rate can be up to 1066MT/s,can input 10 kinds of load type data dynamic cache,designed throughput up to50Gbps.In this paper,the system functions are simulated and verified by Modelsim simulation platform,and the verification results are given.The results show that the design can meet the requirements of multi-load and high rate application.

关 键 词：高速缓存 DDR3 多通道载荷 

分 类 号：TP391.4[自动化与计算机技术—计算机应用技术]