高压非穿通P-i-N二极管等离子体抽取渡越振荡集总电路模型及封装抑制方法研究  

Research on Lumped Circuit Model and Package Suppression Method of Plasma Extraction Transit Time Oscillation in High-voltage NPT P-i-N Diode

作　　者：朱安康 包鑫康 陈宇 周宇 罗皓泽[1] 李武华[1] 何湘宁[1] ZHU Ankang;BAO Xinkang;CHEN Yu;ZHOU Yu;LUO Haoze;LI Wuhua;HE Xiangning(State Key Laboratory of Power Electronics(Zhejiang University),Hangzhou 310027,Zhejiang Province,China)

机构地区：[1]电力电子国家专业实验室(浙江大学),浙江省杭州市310027

出　　处：《中国电机工程学报》2023年第1期263-273,共11页Proceedings of the CSEE

基　　金：国家自然科学基金项目(U1834205,52107211);浙江省“尖兵”“领雁”研发攻关计划(2022C01094)。

摘　　要：高压非穿通P-i-N二极管反向恢复阶段产生等离子抽取渡越时间(plasma extraction transit time,PETT)振荡,对功率模块的驱动电路和设备EMC性能造成严重干扰。文中根据二极管PETT振荡阶段载流子运行特征将器件内部分为等离子区、漂移区和无源区3个区域并将各区域等效成电阻、电感和电容等集总电路参数,利用二极管等效电路与外围电路参数构建了PETT振荡集总电路模型。该模型可计算得到振荡阶段回路各阻抗的动态变化,复现PETT振荡失稳–自稳振荡现象。该集总电路模型表明PETT振荡出现根本原因是回路出现负阻,而负阻出现的原因是空穴渡越角位于π~2π之间,基于该模型解析得到回路寄生电感的优化范围,通过优化封装布局的方式可将空穴渡越角移出负阻出现的区间。最后,在模块内部通过优化绑定线布局将回路寄生电感调整至优化范围内,从而避免回路负阻以抑制PETT振荡的出现,实验证明了该封装抑制方法的有效性。The reverse recovery process of the high-power non-punch through(NPT) P-i-N diode causes plasma extraction transit time(PETT) oscillation, which results in serious interference to the drive circuit and EMC performance. According to the carrier operation characteristics during PETT oscillation stage, the device is divided into three regions: plasma region, drift region and passive region, and each region was equivalent to lumped circuit parameters such as resistance, inductance, and capacitance. The lumped circuit model of PETT oscillation was constructed by combining the equivalent circuit of diode with external circuit parameters. The model can calculate the dynamic variations of each impedance in the loop, and reproduce the instability to self-stable oscillation phenomenon during PETT oscillation stage. The lumped circuit model shows that the fundamental cause of PETT oscillation is the negative resistance in the loop, and the reason for the negative resistance is that the hole transition angle is between π and 2π. Furthermore, the optimal range of loop parasitic inductance was obtained based on the model, which can be realized by optimizing the package layout. Finally, this paper adjusted the loop parasitic inductance to the optimized range by optimizing the layout of bonding wires inside the welded power module to avoid the negative resistance of the loop and suppress the occurrence of PETT oscillation. The experiment proved the effectiveness of the package suppression method.

关 键 词：焊接式模块 非穿通P-i-N二极管 等离子抽取渡越时间振荡 集总电路模型 封装抑制方法 

分 类 号：TN312.4[电子电信—物理电子学]