基于RISC-V的AES密码加速引擎设计与验证  

Design and verification of AES cryptographic acceleration engine based on RISC-V

作　　者：张晓磊 戴紫彬[1] 郭朋飞[1] 李杨[1] Zhang Xiaolei;Dai Zibin;Guo Pengfei;Li Yang(Information Engineering University,Zhengzhou 450001,China)

机构地区：[1]信息工程大学,河南郑州450001

出　　处：《电子技术应用》2023年第2期39-44,共6页Application of Electronic Technique

摘　　要：随着物联网技术的快速发展和物联网设备的广泛部署,信息安全问题日益凸显。密码是保障信息安全的关键核心技术,但传统的密码算法适配方案存在性能和灵活性难以兼顾的问题,提出了一种密码指令扩展方案在两者之间取得了很好的平衡。首先分析了AES算法的运算环节,结合蜂鸟E203处理器架构,提出了密码指令扩展和加速引擎设计方案;接着进行了软硬件实现,构建了RTL级仿真环境和FPGA板级验证环境;最后进行了实验验证和对比分析。实验结果表明,提出的方案在只增加接近2%的硬件资源的情况下可以取得约700%的加速比,具有较高的能效,可适用于在物联网等资源受限的场合。With the rapid development of IoT technology and the widespread deployment of IoT devices,the issue of information security has become increasingly prominent.Cryptography is the key core technology to ensure information security,but the tradi‐tional cryptographic algorithm adaptation scheme is difficult to balance performance and flexibility,this paper proposes a crypto‐graphic instruction extension scheme to achieve a good balance between the two scheme.Firstly,we analyze the computational as‐pects of the AES algorithm,and propose a cryptographic instruction extension and acceleration engine design scheme by combin‐ing the Hummingbird E203 processor architecture;then we complete hardware and software implementation,build an RTL-level simulation environment and an FPGA board-level verification environment;finally,we perform experimental verification and com‐parative analysis.The experimental results show that the proposed scheme can achieve about 700%acceleration ratio with only nearly 2%increase in hardware resources,which has high energy efficiency and can be applied in resource-constrained situations such as IoT.

关 键 词：RISC-V 密码指令扩展 加速引擎 信息安全 

分 类 号：TN47[电子电信—微电子学与固体电子学]