针对直流偏移的三相锁相环改进设计  

A Modified Design of Three-phase Phase-locked Loop for DC Offset

作　　者：文超 苗长新[1] 张远 江蝶 WEN Chao;MIAO Chang-xin;ZHANG Yuan;JIANG Die(China University of Mining and Technology,Xuzhou 221008,China)

机构地区：[1]中国矿业大学,电气工程学院,江苏徐州221008

出　　处：《电力电子技术》2022年第11期27-29,53,共4页Power Electronics

摘　　要：在三相电力系统中,同步参考坐标系锁相环(SRF-PLL)是理想电网条件下最常用的同步技术。然而,直流偏移会导致电网同步信号中出现基频振荡误差。此处设计了一种针对直流偏移的新型三相锁相环(DIANFMAF-PLL),提出一种双改进型自适应陷波器(DIANF)作为环外滤波结构,引入滑动平均值滤波器(MAF)作为环内滤波结构。采用较小的MAF窗口长度,在消除电网电压中直流偏移及谐波分量的同时,缩短了系统的响应时间。实验结果表明,DIANF-MAF-PLL能够有效抑制直流偏移,抗扰动能力强,具有响应速度快和锁相精度高的优点,在恶劣工况下能实现电压信号的零稳态误差跟踪。In three-phase power systems,synchronous reference frame phase-locked loop(SRF-PLL) is the most commonly used synchronization technique under ideal grid conditions.However,the DC offset can cause fundamental frequency oscillation errors in the grid synchronization signal.A novel three-phase phase-locked loop for DC offset(DIANFMAF-PLL) is designed,and a dual-improved adaptive notch filter(DIANF) is proposed as an out-of-loop filtering structure,and a moving average filter(MAF) is introduced as an in-loop filtering structure.Using a smaller MAF window length can shorten the response time of the system while eliminating the DC offset and harmonic components in the grid voltage.The experimental results show that DIANF-MAF-PLL can effectively suppress DC offset and has strong anti-disturbance ability.DIANF-MAF-PLL has the advantages of fast response speed and high phase-locked accuracy,and can achieve zero-steady-state error tracking of voltage signals under severe working conditions.

关 键 词：锁相环 滑动平均值滤波器 自适应陷波器 

分 类 号：TN911.8[电子电信—通信与信息系统]