5G LDPC编码器的低复杂度实现  

Low-Complexity Implementation of 5G LDPC Encoder

作　　者：雷岳俊[1] 王力男[2] 巴晓辉 胡东伟[2] LEI Yuejun;WANG Linan;BA Xiaohui;HU Dongwei(School of information engineering,Minzu University of China,Beijing 100081,China;54th Institute of CETC,Shjiazhuang 050080,China;School of Electronic and Information Engineering,Beijing Jiaotong University,Beijing 100044,China)

机构地区：[1]中央民族大学信息工程学院,北京100081 [2]中国电子科技集团公司第五十四研究所,石家庄050080 [3]北京交通大学电子信息工程学院,北京100044

出　　处：《中央民族大学学报（自然科学版）》2023年第1期47-57,共11页Journal of Minzu University of China(Natural Sciences Edition)

摘　　要：针对5G LDPC编码因校验矩阵个数多、循环块大小取值多而导致编码器实现困难的问题,通过分析、优化由校验矩阵求取校验位的线性变换过程,提出一种面向片上系统(System-On-Chip,SoC)的编码器架构。在该架构下,编码器作为一个加速器,挂在主处理器的数据总线上。编码器包括控制器、基本图存储器、信息/校验位存储器、寄存器文件和3个运算器(移位器、求模器、加法器)。文中提出了基本图的存储方法和格式并对该编码器进行了FPGA实现。结果表明,该编码器具有低复杂度、中等吞吐率的特点。The Low-Density-Parity-Check(LDPC)code for 5G New Radio(NR)specification has multiple parity-check matrices,and multiple different circulant sub-matrix size,which leads to the difficulty of the implementation of the encoder.After analyzing and optimizing of the linear transform process while calculating the parities through the parity-check matrix,a new encoder architecture is proposed.With this architecture,the encoder is attached to the data bus of the main processor as an accelerator,and the encoder is consisted of a controller,a memory for base graph(which defines the parity-check matrix),a memory for information/parity bits,a register file and 3 computational units(these are,a shifter,a mod module and an adder).The method for storing the base graph is proposed.The encoder is implemented on FPGA,which shows that the encoder is with low-complexity and moderate throughput.With 160MHz clock frequency and 1/3 coding rate,the throughput of the encoder could achieve 415Mbps.

关 键 词：5G移动通信 低密度奇偶校验码 编码器 FPGA 

分 类 号：TN915[电子电信—通信与信息系统]