老炼试验中上下拉电阻实例分析  

Example Analysis of Pull-up/Pull-down Resistance in Burn-in Test

作　　者：周杰 周蕾 成锡军 ZHOU Jie;ZHOU Lei;CHENG Xijun(No.58 Research Institute of China Electronics Technology Group Corporation,Wuxi 214035,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《电子质量》2023年第1期87-90,共4页Electronics Quality

摘　　要：在芯片正常运行过程中,需要对特定的IO烧录口进行电平钳制,即保持在高/低电平。为了达到这样的目的,在设计硬件时,需要给烧录口进行上下拉电阻的匹配。从实际中的一个具体项目出发解释了正确使用上下拉电阻对芯片信号的影响和作用。通过查阅相关资料,并结合本次项目试验和经验总结,阐述了上下拉电阻的使用和选择方法,以期能够提高信号稳定性并为硬件设计工程师提供一些帮助或灵感。During the normal operation of the chip, it is necessary to clamp the level of the specific IO burning port,namely it needs to be kept at the high/low level. To achieve this goal, when designing the hardware, it is necessary to match the pull-up and pull-down resistance for the burning mouth. From a specific project in practice, the influence and role of correct use of pull-up and pull-down resistors on chip signals are described. By consulting the relevant information, and combining with the project and experience summary, the use and selection method of pull-up and pull-down resistance are expounded, hoping to improve the stability of the signal, and provide some help or inspiration to the hardware design engineer.

关 键 词：IO 上/下拉电阻 信号 稳定性 电平钳制 

分 类 号：TB114.39[理学—概率论与数理统计]