基于RISC-V架构的中断实验设计  

Interrupt Experiment Design Based on RISC-V Architecture

作　　者：冯建文[1] FENG Jianwen(School of Computer Science and Technology,Hangzhou Dianzi University,Hangzhou 310018,China)

机构地区：[1]杭州电子科技大学计算机学院,杭州310018

出　　处：《实验室研究与探索》2022年第12期34-38,共5页Research and Exploration In Laboratory

基　　金：国家级一流本科课程项目(教高函[2020]8号);浙江省课程思政示范课程项目(浙教函[2021]47号);浙江省高等教育“十三五”教学改革研究项目(jg20190167)。

摘　　要：中断处理是CPU的重要功能,中断原理与设计是计算机组成原理课程的学习难点。基于多周期RISC-V架构,设计了一个功能精简、原理深入的中断实验,实现了能处理单重可屏蔽外部中断的CPU。分析了RISC-V中断机制,为中断CPU设计了一个简单的中断控制器。目标指令集包含8条RV32I基本指令和5条中断相关指令。构造了中断模型机的系统结构,分析了各条指令的数据通路和执行过程,最后基于FPGA完成了设计、仿真测试和板级验证。Interrupt processing is an important function of CPU,and interrupt principle and design are the difficulties in the course of computer composition principle.Based on multi-cycle RISC-V architecture,an interrupt experiment with simplified functions and advanced principles is designed,and a CPU that can handle single maskable external interrupt is realized.RISC-V interrupt mechanism is analyzed,and a simple interrupt controller is designed for interrupt CPU.The target instruction set contains 8 RV32I basic instructions and 5 interrupt related instructions.The system structure of interrupt model machine is constructed,and the data path and execution process of each instruction are analyzed.Finally,the design and implementation,simulation test and board level verification are completed based on FPGA.

关 键 词：中断实验 RISC-V架构 多周期CPU 

分 类 号：TP306[自动化与计算机技术—计算机系统结构]