基于龙芯Local IO接口的UART IP核设计  

Design of UART IP Core Based on Loongson Local IO Interface

作　　者：李森 李中 袁强 唐建 LI Sen;LI Zhong;YUAN Qiang;TANG Jian(Department of Special ComputerAutomation Research Institute Co.,Ltd.,China Ordnance Equipment Group,Mianyang 621000,China)

机构地区：[1]中国兵器装备集团自动化研究所有限公司特种计算机事业部,四川绵阳621000

出　　处：《智能物联技术》2022年第5期1-7,共7页Technology of Io T& AI

摘　　要：针对龙芯系列CPU自带UART(Universal Asynchronous Receiver Transmitter)接口有限且Xilinx UART IP核与龙芯Local IO接口的不兼容问题,本文设计了一种适配龙芯CPU Local IO接口的UART IP核。该IP核能够直接挂载到Local IO接口上,实现龙芯CPU UART接口的扩展;利用发送FIFO与接收FIFO,实现串口数据的自动收发;通过设计接收阈值机制与接收超时机制,降低了中断触发的频率,杜绝了CPU频繁进入中断的情况。最后,在FPGA上进行设计实现,经过实际测试,该IP核实现了需求的功能,且性能稳定。Aiming at the limited UART interface of Loongson series CPU and the incompatibility between xilinx UART IP core and Loongson Local IO interface,a UART IP core adapted to Loongson CPU Local IO interface is designed.The IP core can be directly mounted on the Local IO interface to realize the expansion of the Loongson CPU UART interface;use the sending FIFO and the receiving FIFO to realize the automatic reception of serial data;by designing the receiving threshold mechanism and the receiving timeout mechanism,the frequency of interruption triggered by the interrupt is reduced,which prevents the CPU from frequently entering interrupts.Finally,the design and implementation are carried out on FPGA.After actual testing,the IP core realizes the required functions and has stable performance.

关 键 词：龙芯CPU Local IO接口 UART IP FPGA 

分 类 号：TP368[自动化与计算机技术—计算机系统结构]