List-Serial Pipelined Hardware Architecture for SCL Decoding of Polar Codes  

作　　者：Zhongxiu Feng Cong Niu Zhengyu Zhang Jiaxi Zhou Daiming Qu Tao Jiang 

机构地区：[1]Research Center of 6G Mobile Communications,School of Cyber Science and Engineering,and Wuhan National Laboratory for Optoelectronics,Huazhong University of Science and Technology,Wuhan 430074,China [2]Institute of Space Integrated Ground Network,Hefei 230094,China [3]The 38th Research Institute of China Electronics Technology Group Corporation,Hefei 230088,China [4]School of Electronics Information and Communications,Huazhong University of Science and Technology,Wuhan 430074,China

出　　处：《China Communications》2023年第3期175-184,共10页中国通信（英文版）

基　　金：supported in part by the National Key R&D Program of China(No.2019YFB1803400)。

摘　　要：For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.

关 键 词：successive cancellation list decoding po-lar codes hardware implementation pipelined archi-tecture 

分 类 号：TN911.22[电子电信—通信与信息系统]