一种基于FPGA的可配置机箱并行总线技术  

A FPGA-based Configurable Chassis Parallel Bus Technology

作　　者：凡林斌 李淼 谭磊 FAN Linbin;LI Miao;TAN Lei(CRRC Zhuzhou Institute Co.,Ltd.,Zhuzhou,Hunan 412001,China)

机构地区：[1]中车株洲电力机车研究所有限公司,湖南株洲412001

出　　处：《控制与信息技术》2023年第1期84-89,共6页CONTROL AND INFORMATION TECHNOLOGY

基　　金：湖南省教育厅科学研究项目(21C0430)。

摘　　要：现有部分应用场景中,工业控制平台对机箱并行总线数据空间管理具有拓展性需求。对此,文章提出了一种可灵活配置、高效拓展的机箱并行总线技术方案。其通过从已有总线地址空间内分离出配置空间,并利用配置空间的功能分区实现了设备的即插识别、数据空间动态分配、紧急广播和端口数据传输等功能;同时搭建了基于并行总线的多插件式机箱硬件环境,并采用具备现场可编程逻辑门阵列(FPGA)器件的插件对该技术方案进行了功能测试及验证工作。测试结果显示,机箱的各项功能正常,表明该并行总线技术完全能够基于FPGA实现功能设计目标。该总线方案在某项目进行了为期半年的运行考核,结果显示,总线运行正常,进一步证实了该方案的有效性。In some existing application scenarios, industrial control platforms have expandable requirements for the data space management of chassis parallel bus. In this paper, a new chassis parallel bus technology scheme that can be flexibly configured and efficiently expanded is proposed. By separating the configuration space from the existing bus address space, the function partition of the configuration space is used to realize the functions of device plug identification, data space dynamic allocation, emergency broadcast, port data transmission, etc. At the same time, the hardware environment of multiple plug-in chassis based on parallel bus is built, and the functional test and verification of the technical scheme are carried out by using plug-ins with field programmable gate array(FPGA) devices. The test results show that all functions are normal, indicating that the parallel bus technology completely achieve the functional design goal based on FPGA. In addition, the bus scheme has completed a half-year operation assessment in the practical application scenario of special projects, and the bus runs normally, further verifying the effectiveness of the scheme.

关 键 词：并行总线 数据管理 现场可编程逻辑门阵列(FPGA) 配置空间 通信系统 工业控制系统 

分 类 号：TN91[电子电信—通信与信息系统]