基于FPGA的HEVC去方块滤波硬件设计  

Hardware Design of HEVC Deblocking Filtering Based on FPGA

作　　者：陈焯淼 陈志峰[1] 陈建[1] 汪家华 CHEN Zhuomiao;CHEN Zhifeng;CHEN Jian;WANG Jiahua(College of Physics and Information Engineering,Fuzhou University,Fuzhou 350108,China)

机构地区：[1]福州大学物理与信息工程学院,福建福州350108

出　　处：《电视技术》2023年第1期48-51,69,共5页Video Engineering

基　　金：国家自然科学基金(62001117)。

摘　　要：去方块滤波(Deblocking Filtering,DBF)是高效视频编码(High Efficiency Video Coding,HEVC)的重要组成部分,能够有效地改善编码图像的主观质量,是提升视频整体编码性能的重要手段之一。但是去方块滤波技术复杂度较高。为解决该问题,设计一种HEVC去方块滤波器的硬件架构,在节省资源消耗的同时,减少处理周期并改善滤波效率。以8×4块为基本滤波单元,从输入像素到输出像素,采用四级流水线的形式进行处理,每处理一个基本滤波单元共花费5个周期。实验结果表明,所设计的去方块滤波器仅需5 212个查找表和1 291个寄存器的逻辑资源消耗,最高可达到215 MHz的工作频率,满足1 080p@60fps的高清视频实时编码。Deblocking Filtering(DBF) is an important part of High Efficiency Video Coding(HEVC), which can effectively improve the subjective quality of encoded images and it is one of the important means to improve overall video encoding performance. However,the complexity of deblocking filtering technology is relatively high. To solve this problem, this paper designs a HEVC deblocking filter hardware architecture, which not only saves resource consumption, but also reduces the processing cycle and improves the filtering efficiency. Taking 8×4 blocks as the basic filtering unit, from input pixels to output pixels, a four-stage pipeline is used for processing.Each basic filtering unit takes 5 cycles in total. The experimental results show that the deblocking filter only needs 5 212 lookup tables and 1 291 registers, and the operating frequency can reach up to 215 MHz, which meets the real-time coding of HD video at 1 080p@60fps.

关 键 词：去方块滤波(DBF) 高效视频编码(HEVC) 环路滤波 

分 类 号：TP311.5[自动化与计算机技术—计算机软件与理论]