一种具有时标对齐功能的存储器设计  

A memory design with time scale alignment function

作　　者：林天鹏 陈辉 张彦军[1] 翟成瑞[1] LIN Tianpeng;CHEN Hui;ZHANG Yanjun;ZHAI Chengrui(State Key Laboratory of Dynamic Measurement Technology,North University of China,Taiyuan 030051,China;Beijing Aerospace System Engineering Institute,Beijing 100076,China)

机构地区：[1]中北大学省部共建动态测试技术国家重点实验室,山西太原030051 [2]北京宇航系统工程研究所,北京100076

出　　处：《电子设计工程》2023年第7期165-168,174,共5页Electronic Design Engineering

摘　　要：大型装备在实验中获得的数据对后续设备的研究及改进有着重要意义,因此获得可靠有效的实验数据至关重要。该文提出了一种基于FPGA的数据存储器设计,通过工作模式、接口电路、时标对齐及存储逻辑等的设计,实现了对多路数据的可靠存储。经实验验证,该存储器时序控制合理、工作状态可靠,能够满足高可靠性的实验数据获取要求,对装备的研发及改进有着重要的参考依据。The data obtained in the experiment of large equipment is of great significance to the research and improvement of subsequent equipment,so it is very important to obtain effective experimental data reliably.This paper presents a design of multi⁃mode data memory based on FPGA.Through the design of working mode,interface circuit,time scale alignment and storage logic,the reliable storage of multi⁃channel data is realized.The experimental results show that the memory has reasonable timing control and reliable working state,can meet the requirements of high reliability test data acquisition,and has an important reference basis for the reseach&development and improvement of equipment.

关 键 词：数据存储器 FPGA 时标对齐 无效块检查 

分 类 号：TN492[电子电信—微电子学与固体电子学]