基于SOPC技术的芯片批量测试板设计与实现  

Design and Implementation of Chip Batch Testing Board Based on SOPC Technology

作　　者：易凡 马静怡 YI Fan;MA Jingyi(Zhengzhou University of Science and Technology,Zhengzhou 450064,China)

机构地区：[1]郑州科技学院,河南郑州450064

出　　处：《现代信息科技》2023年第6期88-91,共4页Modern Information Technology

摘　　要：为提高SoC芯片测试板效率及稳定性,考虑芯片测试需求和设计模块化等因素,采用可编程片上系统和上位机配置技术,充分利用FPGA开发板上的HSTC扩展接口,设计了一款面向多芯片同步测试的批量测试板,有效解决了芯片批量测试中的难题,实现效率与性能的双优。主要阐述了该测试板的上位机控制方法、嵌入式控制系统的功能组成以及片上测试程序的设计流程。To improve the efficiency and stability of SoC chip testing board,this paper considers the testing requirement of chip and the modular design and other factors,uses System on Programmable Chip(SOPC)and master computer configuration technology,makes full use of the HSTC expansion interfaces of FPGA development board,designs a batch testing board for multi-chip synchronization testing.It effectively solves the difficult problems in the chip batch testing,and realizes both efficiency and stability.This paper mainly expounds the master computer control method of the testing board,the functional composition of the embedded control system and the design process of the testing program on the chip.

关 键 词：SOC 批量测试 现场可编程门阵列 上位机 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论] TN407[自动化与计算机技术—计算机科学与技术]