基于EDA技术的常用串口通信总线接口逻辑设计  

Logic design of common serial communication bus interface based on EDA technology

作　　者：杨奇 刘红[1] 李斌 YANG Qi;LIU Hong;LI Bin(Energy and Control Engineering College,Changji University,Changji 831100,China)

机构地区：[1]昌吉学院能源与控制工程学院,新疆昌吉831100

出　　处：《现代电子技术》2023年第7期22-26,共5页Modern Electronics Technique

基　　金：昌吉学院校级教研项目(21JYYB005)。

摘　　要：新兴技术发展对通信总线接口性能提出了更高的要求,再加之接口之间交互行为的剧增,常规通信总线接口资源占用率过高、传输速度过低等缺陷逐渐显现。为了改善上述情况,提出基于EDA技术的常用串口通信总线接口逻辑设计。引入EDA技术搭建接口逻辑设计框架,以此为基础,选取适当的实现器件——FPGA控制器,设计具体数字接口(RS 232接收模块、I2C接收模块与SPI接收模块),并设计接口协议层(CRC校验、NRZI解码及其去除位填充),通过上述过程完成了常用串口通信总线接口的逻辑设计。实验数据表明,所设计接口资源占用率数值范围为19.58%~30.12%,传输速率最大值为48 Mb/s,达到预期接口设计目标。The development of emerging technologies has put forward higher requirements for the performance of communication bus interfaces.In addition to the sharp increase in the interaction between interfaces,the defects such as high resource occupancy rate and low transmission speed of conventional communication bus interfaces have gradually emerged.In order to improve the above situation,the research on the EDA technology based logic design of common serial communication bus interface is proposed.The EDA technology is introduced to build the interface logic design framework.On this basis,the appropriate device(FPGA controller)is selected.The specific digital interfaces for RS 232 receiving module,I2C receiving module and SPI receiving module,and the interface protocol layer for CRC verification,NRZI decoding and its removal bit filling are designed.The logic design of the common serial communication bus interface is completed after the above process.The experimental data shows that the designed interface′s resource utilization ratio is 19.58%~30.12%,and the maximum transmission rate is 48 Mb/s,which meets the expected interface design goal.

关 键 词：接口设计 串口通信总线 EDA技术 接口逻辑设计 FPGA控制器 接口协议层设计 

分 类 号：TN913.3-34[电子电信—通信与信息系统] TP241[电子电信—信息与通信工程]