具有快速锁定时间的ADPLL电路设计  

ADPLL circuit design with fast lock time

作　　者：王巍[1] 张涛洪 刘斌政 赵汝法 袁军[1] WANG Wei;ZHANG Taohong;LIU Binzheng;ZHAO Rufa;YUAN Jun(College of Electronics Engineering/International Semiconductor College,Chongqing University of Posts and Telecommunications,Chongqing 400065,China)

机构地区：[1]重庆邮电大学光电工程学院/国际半导体学院,重庆400065

出　　处：《微电子学与计算机》2023年第4期95-100,共6页Microelectronics & Computer

基　　金：重庆市科技局科技重大专项(cstc2018jszx-cyztzx0211,cstc2018jszx-cyztzxX0054);重庆市教委项目(KJQN201800628)。

摘　　要：快速锁定是全数字锁相环(ADPLL)的关键指标之一.在理想情况下,锁定时间应尽可能短.传统结构ADPLL(TS-ADPLL)通常使用自适应带宽技术或数控振荡器(DCO)调谐字和预设技术来减少锁定时间.然而,自适应带宽技术和预设技术都需要额外的模块,这将增加额外的功耗.为了提升全数字锁相环的锁定速度,本文提出了一种基于高分辨时间数字转换器(TDC)快速锁定的全数字锁相环(ADPLL)电路.其中,TDC电路采用双级触发器和抽头延迟链相结合的结构,不仅提升了电路对信号的容纳程度,还提高了量化误差信号的分辨率以及电路的锁定速度.同时,通过双SR锁存器完成对参考信号超前或滞后的鉴定,可以更好的检测参考信号与输出信号的相位关系,利于系统对输出信号的相位调整及信号的锁定.采用XILINX Artix-7 FPGA器件进行验证仿真.仿真结果表明,该ADPLL的锁定时间可达3.9μs,其锁定范围为4.7 MHz~35.7 MHz.该ADPLL电路具有锁定速度快,锁定范围大等特点.Fast locking is one of the key metrics of an all-digital phase-locked loop(ADPLL).Ideally,the lockout time should be as short as possible.Traditionally structured ADPLL(TS-ADPLL)typically use adaptive bandwidth techniques or numerically controlled oscillator(DCO)tuning words and preset techniques to reduce lock time.However,both adaptive bandwidth technology and preset technology require additional modules,which will add additional power consumption.In order to improve the locking speed of the all-digital phase-locked loop,an all-digital phase-locked loop(ADPLL)circuit based on high-resolution time-to-digital converter(TDC)for fast locking is proposed in this paper.Among them,the TDC circuit adopts a structure combining a double-stage flip-flop and a tapped delay chain,which not only improves the signal tolerance of the circuit,but also improves the resolution of the quantization error signal and the locking speed of the circuit.At the same time,the identification of the lead or lag of the reference signal is completed through the dual SR latches,which can better detect the phase relationship between the reference signal and the output signal,which is beneficial to the system's phase adjustment of the output signal and signal locking.The verification simulation is carried out using XILINX Artix-7 FPGA device.The simulation results show that the locking time of the ADPLL can reach 3.9μs,and its locking range is 4.7 MHz~35.7 MHz.The ADPLL circuit has the characteristics of fast locking speed and large locking range.

关 键 词：时间数字转换器 快速锁定 全数字锁相环 

分 类 号：TN402[电子电信—微电子学与固体电子学]