SoC芯片上AHB总线矩阵的设计及验证  

Design and verification of AHB bus matrix on SoC chip

作　　者：朱峰 刘威 ZHU Feng;LIU Wei(School of Physics and Technology,Wuhan University,Wuhan 430072,China;Hubei Luojia Laboratory,Wuhan 430072,China;Shenzhen Research Institute of Wuhan University,Shenzhen 518057,Guangdong Province,China)

机构地区：[1]武汉大学物理科学与技术学院,武汉430072 [2]湖北珞珈实验室,武汉430072 [3]武汉大学深圳研究院,广东深圳518057

出　　处：《信息技术》2023年第3期1-5,12,共6页Information Technology

基　　金：科技助力经济2020重点专项(SQ2020YFF0426493);武汉市应用基础前沿项目(2019010701011386);深圳市知识创新计划基础研究项目(JCYJ20180302173424902);湖北珞珈实验室专项基金资助项目(220100025)。

摘　　要：随着SoC的复杂度不断提高,通过集成IP核的设计方式能够加快芯片设计的周期,同时由于总线上主从设备的增加,有必要基于AHB总线设计一款高速互连的AHB总线矩阵,在AHB multi layer的基础上,将仲裁模块改为由内部寄存模块接收信息后,再由从机端完成对各个主机发送过来的信号信息进行仲裁。同时还加入了防死锁模块,从而实现了能够根据预设的计数阈值判断AHB是否发生死锁的功能;最后通过AHB总线接口的验证IP搭建UVM仿真测试环境,对所设计的总线系统基本功能进行了测试,实现了单master访问多个slave和多个master对多个slave并行访问的功能。As the complexity of SoC continues to increase,the design method of integrating IP cores can speed up the chip design cycle.At the same time,due to the increase of master-slave devices on the bus,it is necessary to design a high-speed interconnected bus matrix based on the AHB bus.On the basis of the AHB multi layer,after the arbitration module is changed to receive information from the internal register module,the slave side completes the arbitration of the signal information sent by each host.At the same time,an anti-deadlock module is also added,so as to realize the function of judging whether AHB deadlock occurs according to the preset count threshold.Finally,the function has been tested,and the functions of single master accessing multiple slaves and multiple masters accessing multiple slaves in parallel are realized.

关 键 词：AHB总线矩阵 交叉互联 片上系统 并行访问 UVM 

分 类 号：TN492[电子电信—微电子学与固体电子学]