基于硬件逻辑语言的数字频率计设计  

Design of Digital Frequency Meter Based on Hardware Logic Language

作　　者：金诗雨 杨晓宇 于馨淼 郑馥钰 胡明月 王颖[1] Jin Shiyu;Yang Xiaoyu;Yu Xinmiao;Zheng Fuyu;Hu Mingyue;Wang Ying(City Institute,Dalian University of Technology,Dalian 116100,China)

机构地区：[1]大连理工大学城市学院,大连116100

出　　处：《单片机与嵌入式系统应用》2023年第4期50-53,共4页Microcontrollers & Embedded Systems

摘　　要：针对目前在航空航天、电子技术、测控等技术领域遇到的问题,数字频率计能够准确、快速地捕捉到信号频率的变化。本文重点介绍了如何运用EDA技术来实现数字频率计的设计,采用基础开发软件并采用Verilog HDL语言进行编译,Waveform进行了波形图仿真,最后设计了顶层文件图。Focusing on solving the problems encountered in the technical fields of aerospace,electronic technology,measurement and control,etc.,the digital frequency meter can accurately and quickly capture the change of signal frequency.Therefore,this article focuses on the use of EDA technology to realize the design of digital frequency meter,using basic development software and using Verilog HDL language to compile,waveform carried out waveform simulation,and finally designed the top-level file diagram.

关 键 词：EDA Verilog HDL QuartusⅡ 

分 类 号：TP31[自动化与计算机技术—计算机软件与理论]