Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm  

作　　者：Mohanapriya Marimuthu Santhosh Rajendran Reshma Radhakrishnan Kalpana Rengarajan Shahzada Khurram Shafiq Ahmad Abdelaty Edrees Sayed Muhammad Shafiq 

机构地区：[1]Department of CSE,Coimbatore Institute of Technology,Coimbatore,641014,India [2]Department of CSE,Karpagam Academy of Higher Education,Coimbatore,641021,India [3]Department of Electronics and Communication Engineering,Veltech Multitech Dr.Rangarajan Dr.Sakunthala Engineering,Chennai,600062,India [4]Faculty of Computing,The Islamia University of Bahawalpur,Bahawalpur,63100,Pakistan [5]Industrial Engineering Department,College of Engineering,King Saud University,P.O.Box 800,Riyadh,11421,Saudi Arabia [6]Department of Information and Communication Engineering,Yeungnam University,Gyeongsan,38541,Korea

出　　处：《Computers, Materials & Continua》2023年第3期4729-4745,共17页计算机、材料和连续体（英文）

基　　金：This work was supported by King Saud University for funding this work through Researchers Supporting Project number(RSP-2021/387),King Saud University,Riyadh,Saudi Arabia。

摘　　要：Continuous improvements in very-large-scale integration(VLSI)technology and design software have significantly broadened the scope of digital signal processing(DSP)applications.The use of application-specific integrated circuits(ASICs)and programmable digital signal processors for many DSP applications have changed,even though new system implementations based on reconfigurable computing are becoming more complex.Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation(DWT)and sophisticated computerized design techniques,which are much needed in today’s modern world.New research and commercial efforts to sustain power optimization,cost savings,and improved runtime effectiveness have been initiated as initial reconfigurable technologies have emerged.Hence,in this paper,it is proposed that theDWTmethod can be implemented on a fieldprogrammable gate array in a digital architecture(FPGA-DA).We examined the effects of quantization on DWTperformance in classification problems to demonstrate its reliability concerning fixed-point math implementations.The Advanced Encryption Standard(AES)algorithm for DWT learning used in this architecture is less responsive to resampling errors than the previously proposed solution in the literature using the artificial neural networks(ANN)method.By reducing hardware area by 57%,the proposed system has a higher throughput rate of 88.72%,reliability analysis of 95.5%compared to the other standard methods.

关 键 词：VLSI A ES discrete wavelet transformation signal processing 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]