High-Bandwidth,Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array  

作　　者：Ameen Bin Obadi Alaa El-Din Hussein Samir Salem Al-Bawri Kabir Hossain Abdullah Abdulhameed Muzammil Jusoh Thennarasan Sabapathy Ahmed Jamal Abdullah Al-Gburi Mahmoud A.Albreem 

机构地区：[1]Advanced Communication Engineering(ACE),Centre of Excellence,Universiti Malaysia Perlis(UniMAP),Faculty of Electronic Engineering Technology,Kangar,01000,Malaysia [2]Electrical Engineering,King Fahd University of Petroleum and Minerals,Dhahran,Eastern,31261,Saudi Arabia [3]Space Science Centre,Climate Change Institute,Universiti Kebangsaan Malaysia,Bangi,43600,Malaysia [4]Department of Electronics&Communication Engineering,Faculty of Engineering&Petroleum,Hadhramout University,Al-Mukalla,Hadhramout,50512,Yemen [5]Faculty of Engineering,Norwegian University of Science and Technology(NTNU),Gjovik,N-2815,Norway [6]Faculty of Electronic Engineering Technology,Universiti Malaysia Perlis(UniMAP),Kampus Alam UniMAP Pauh Putra,Arau,02600,Malaysia [7]Department of General Educational Development,Faculty of Science and Information Technology(FSIT),Daffodil International University,Dhaka,1207,Bangladesh [8]Department of Electronics and Computer Engineering(FKEKK),Center for Telecommunication Research and Innovation(CeTRI),Universiti Teknikal Malaysia Melaka(UTeM),Durian Tungal,76100,Malaysia [9]Department of Electrical Engineering,University of Sharjah,Sharjah,27272,United Arab Emirates

出　　处：《Computers, Materials & Continua》2023年第3期5885-5900,共16页计算机、材料和连续体（英文）

基　　金：This work was supported in part by the Geran Galakan Penyelidik Muda Grant(GGPM),Universiti Kebangsaan Malaysia,Selangor,Malaysia under grant GGPM-2021-055.

摘　　要：This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.

关 键 词：CMOS field programmable analog array configurable analog block current mode circuit 

分 类 号：TP311[自动化与计算机技术—计算机软件与理论]