基于UltraScaleFPGA的高速以太网接口设计与验证  

Design and Verification of High-speed Ethernet Interface Based on UltraScale FPGA

作　　者：崔钟允 姬利 CUI Zhongyun;JI Li(AViC Xi'an Institute of Aeronautical Computing Technology,Shaanxi 710068,China)

机构地区：[1]中国航空工业集团公司西安航空计算技术研究所,陕西710068

出　　处：《电子技术（上海）》2023年第2期34-36,共3页Electronic Technology

摘　　要：阐述UltraScale FPGA高速以太网接口的硬件设计要求,高速以太网接口的硬件设计,根据10G以太网信号完整性要求进行高速信号仿真。探讨信号完整性仿真,优化高速信号PCB设计。This paper describes the hardware design requirements of the UltraScale FPGA highspeed Ethernet interface, the hardware design of the high-speed Ethernet interface, and the highspeed signal simulation according to the 10G Ethernet signal integrity requirements. It discusses signal integrity simulation and optimizes high-speed signal PCB design.

关 键 词：高速接口 FPGA 通信网络 

分 类 号：TN911[电子电信—通信与信息系统]