基于JTAG的高效调试系统设计与实现  

Design and implementation of high performance debugging system based on JTAG

作　　者：张梅娟 辛昆鹏 王丽娟 邓佳伟 Zhang Meijuan;Xin Kunpeng;Wang Lijuan;Deng Jiawei(The Fifty-Eighth Research Institute of China Electronic Technology Group Corporation,Wuxi 214063,China)

机构地区：[1]中国电子科技集团公司第五十八研究所,江苏无锡214063

出　　处：《电子技术应用》2023年第4期39-43,共5页Application of Electronic Technique

摘　　要：为了给自研处理器芯片提供一种高效方便的调试方法,提出了一种基于JTAG的片内调试系统设计方法。该调试系统在遵循JTAG标准协议的基础上,简化片内调试硬件模式设计,以较少的硬件开销和精简高效的专用调试指令设计,不仅实现了调试中断、指令/数据断点设置、单步执行及寄存器/存储器数据读写等基本调试功能,还支持现场保护与恢复、Trace Buffer、指令插入执行等高级调试功能。经实际芯片测试证明,该调试系统具有兼容JTAG协议、功能全面、灵活高效、结构简单、便于操作等特点。A debugging system based on JTAG interface is proposed in this paper to provide an effective and convenient debugging method for domestic processor chip.The debugging system,which is based on JTAG standard,simplifies the design of the on-chip debugging hardware module.With little hardware overhead,simple and high performance design of the debugging instruction,it is used to realize the debugging interrupt,breakpoint and watch point setting,single step running,register or memory read and write,and other base debugging functions,as well as sence protection and recovery,trace buffer,instruction insert execution and other advanced debugging functions.After passed the actual chip testing,the debugging system has compatibility with JTAG protocol,comprehensive functions,high performance,simple structure,convenient for operation and other features.

关 键 词：调试系统 JTAG接口 IEEE1149.1 TAP控制器 

分 类 号：TN407[电子电信—微电子学与固体电子学]